Abstract: A low voltage, high-gain current/voltage sense amplifier (ISA/VSA) circuit with improved read access time is provided herein. According to one embodiment, the ISA/VSA described herein includes a pair of current reference branches for generating a pair of reference currents in response to a pair of differential input signals supplied thereto. The differential input signals are differential voltages which are converted to differential currents by the current reference branches. In some cases, the current reference branches may be used for amplifying and mirroring the reference currents onto output nodes of the ISA/VSA. In doing so, the current reference branches may increase the amplification and improve the performance of the sense amp circuit, even under extreme mismatch conditions. In addition, positive feedback may be used within the ISA/VSA design to further increase the amplification and speed of the sense operation.

Abstract: A method and apparatus for configuring a microcontroller. An XML description of the microcontroller's hardware resources may be accessed. A user may select from available hardware resources and pre-defined user modules to select a configuration. Configuration information, which may include register bit patterns and microprocessor instructions, may be automatically generated. Additionally, application programming interface calls and structure, as well as interrupt vector tables may be automatically generated. Embodiments of the present invention provide improved ease of use and the ability to manage greater complexity in the configuration of configurable microcontrollers.

Abstract: In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the substrate to allow heat to be conducted away from the backside of the die to a top most metal layer of the substrate. Thermal balls may be attached to the bottom side of the substrate on the same plane as the die.

Abstract: Synchronous SRAM may conform to Std. Sync or early-write at an external interface whilst providing late-write internally.

Abstract: A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to reduce a gain. The differential stage (202) and cross-coupled stage (204) can include variable currents sources (208 and 212), respectively. As frequency of operation increases, variable current source (208) provides a larger current to the differential stage (202) and variable current source (212) provides a smaller current to cross-coupled stage (204). Delay cell circuit (200) may be used in a voltage controlled oscillator (VCO). By including gain attenuating devices such as resistors (210-0 and 210-1), a frequency tuning range of the VCO may be increased.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes comparison logic to compare received data values to an expected data value, producing a first result. The apparatus also includes combinatorial logic coupled to the comparison logic. The combinatorial logic is to use the first result to encode in a second result which path of a set of paths the received data should traverse. The apparatus also includes transfer logic coupled to the combinatorial logic. The transfer logic is to transfer the received data values to each of three paths using the second result.

Abstract: A method of making a semiconductor structure, comprises cleaning a gate stack with a cleaning solution. The gate stack comprises a gate layer, a metallic layer on the gate layer, and a etch-stop layer on the metallic layer. The gate layer is on a semiconductor substrate, the cleaning solution is a non-oxidizing cleaning solution, and the metallic layer comprises an easily oxidized metal.

Abstract: In one arrangement, a memory device (100) can include a number of banks (102-0 to 102-2n) and corresponding counters (104-0 to 104-2n). In response to a corresponding active access signal, each counter (104-0 to 104-2n) can generate a bank available indication (BA0 to BA-2n) that may be initially inactive, and remain inactive during an initial count operation. Once a counter (104-0 to 104-2n) reaches a predetermined limit, the corresponding bank available indication (BA0 to BA-2n) can be activated. A count limit can correspond to a minimum active-to-active timing parameter (TRC). An output circuit 106 can provide output data BA_DATA representative of bank available indications (BA0 to BA-2n).

Abstract: Output driver circuits and related methods. In one example, the output driver circuit includes a translator for converting the single ended data input signal into a pair of signals; a set of output transistors selectively controlled by the pair of signals; a cascode current source for providing a substantially constant current to the set of output transistors when the output transistors are active; and a dump path in parallel with the set of output transistors. A circuit portion for pre-charging the pair of signals to a pre-charged voltage between VCC and ground may also be provided.

Abstract: A circuit for generating a reference current, comprising a positive feedback loop, a negative feedback loop, and a floating current mirror coupled to the positive feedback loop. The negative feedback loop may operate to divert current directly from the floating mirror, and may also operate to divert current from the floating mirror by using a voltage follower. The circuit may operate with a minimum supply voltage of approximately the sum of the threshold voltage of a transistor plus three drain saturation voltages, in one example.

Abstract: An apparatus, method, and system for coupling a host computer to a peripheral device over an extended distance. In one example, a first hub is provided for coupling with the host computer, the first hub configured as a compound device including a hub function and an embedded function, the first hub configured such that the embedded function is a virtual hub thereby providing an additional amount of time for signal transmissions by the first hub. A communications link is provided for coupling the first hub with the peripheral device, the characteristics of the communications link being based in part on the additional amount of time made available by the configuration of the first hub.

Abstract: In one embodiment, a sample of an integrated circuit device is prepared for observation in a transmission electron microscope (TEM). The sample may be placed on a surface formed by vertical edges of several TEM grids. The sample may be affixed to a vertical edge of one of the TEM grids. The TEM grid supporting the sample may be separated from the other TEM grids, and then placed in the TEM so that the sample may be observed.

Abstract: A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.

Abstract: An integrated circuit packaging device includes a laminate substrate. A first surface of the substrate can be mounted on an integrated circuit and the second surface can be mounted on a surface of a printed circuit board. The device can also include an array of lead contact pads on the first surface that can provide wire bond connections to circuit contact pads in the integrated circuit, and an array of solder ball contact pads on the second surface. Routing layers can provide electrical coupling between the lead contact pads on the first surface and the solder ball contact pads on the second surface. A dedicated contact pad on the first surface is electrically coupled to the laminate substrate.

Abstract: A method and system for providing hybrid clock distribution is disclosed. The distribution architecture uses a grid distribution at the top level and a balanced buffer tree distribution at the block level. The method includes determining the block layout of an integrated circuit which employs a clock distribution network for distributing clock signals. In addition the method includes providing a mesh distribution network for delivering clock signals to integrated circuit blocks of the integrated circuit. Thereafter, a balanced tree distribution network for delivering clock signals to the components of each block of the integrated circuit is provided. The top level grid provides predictable min/max skew at the top level and the remainder skew budget can be applied to the blocks.

Abstract: An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.

Abstract: A lock-aid circuit and method is applied to a phase lock loop (PLL) having a voltage controlled oscillator (VCO), wherein the lock aid is coupled with the input of the VCO. In one example, the lock aid includes a Schmitt trigger having an output, a switch having an output and an input coupled to the output of the Schmitt trigger, and a voltage controlled current source coupled with the output of the switch.

Abstract: An electronic containment battery includes a battery section and an electronic section that together form a standard battery form factor that allows insertion into conventional electronic devices. The electronic section can include Radio Frequency (RF) circuitry that enables electronic operations in the electronic containment battery to be communicated or controlled wirelessly.

Abstract: A method and apparatus to provide electrostatic discharge (ESD) protection to electronic circuits using a gate clamp circuit.

Abstract: In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.