Abstract: In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

Abstract: A technique for receiving an error state in a single chip sequence in a wireless communications network is disclosed. The error state may comprise a Viterbi error state. The error state may be identified as a target code encoded in the single chip sequence, the target code comprising either a code or the complement of the code. The code may comprise a PN-Code. The error state may be identified using a previous mapping of error states from a set of error states to a group of codes, the group of codes comprising a plurality of codes and their complements. The error states in the set of error states in the previous mapping may be uniquely mapped to plurality of codes and their complements in the group of codes.

Abstract: A method of making a semiconductor structure includes depositing a nitride layer, on a metallic layer, by PECVD. The metallic layer is on a gate layer containing silicon, and the gate layer is on a semiconductor substrate.

Abstract: In one embodiment, an antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse may comprise a capacitor. In another embodiment, current used to program an antifuse cell is controlled using a programming current regulator. The programming current regulator may include components that form a current mirror with components of the antifuse cell to tightly control programming current through the antifuse. In yet another embodiment, dynamic current flowing through a substrate of an antifuse cell is limited using a current limiting resistor directly in series with an antifuse of the antifuse cell. The current limiting resistor minimizes or prevents excessive programming current.

Abstract: A semiconductor detector of electromagnetic radiation which utilizes a dual-purpose electrode which extends significantly beyond the edge of a photodiode. This configuration reduces the sensitivity of device performance on small misalignments between manufacturing steps while reducing dark currents, kTC noise, and “ghost” images. The collection-mode potential of the dual-purpose electrode can be adjusted to achieve charge confinement and enhanced collection efficiency, reducing or eliminating the need for an additional pinning layer. Finally, the present invention enhances the fill factor of the photodiode by shielding the photon-created charge carriers formed in the substrate from the potential wells of the surrounding circuitry.

Abstract: In one embodiment, a level in a process technology for an integrated circuit that has dummy metal patterns is represented as a level in a process model. The level of the process model may comprise a high-k dielectric to represent the dummy metal patterns. In the level of the process model, each metal line may be surrounded by a normal dielectric. If the process technology has voids or pockets of air in between the metal lines, then each void or air pocket may be placed in a normal dielectric in the process model. Among other advantages, this allows the process model to take into account the effects of the dummy metal patterns.

Abstract: A technique for implementing a center key in a capacitive sense radial slider interface without use of center mechanical button. A user interaction with an array of capacitive sensors within the radial slider interface is sensed. It is determined whether at least a threshold number greater than one of the capacitive sensors within the array are concurrently actuated by the user interaction. A center key actuation is registered if at least the threshold number of the capacitive sensors are concurrently actuated.

Abstract: A method for processing a semiconductor topography which includes removing metal oxide layers from the bottom of contact openings is provided. In some embodiments, the method may include etching openings within a dielectric layer to expose conductive and silicon surfaces within the semiconductor topography is provided. In such cases, the method further includes exposing the semiconductor topography to an etch process adapted to remove metal oxide material from the conductive surfaces without substantially removing material from the silicon surfaces. In some cases, the etch chemistry used for the etch process may include sulfuric acid. In addition or alternatively, the etch chemistry may include hydrogen peroxide. In any case, the etch chemistry may be distinct from chemistries used to remove residual matter generated from the etch process used to form the openings within the dielectric and/or the removal of the masking layer used to pattern the openings.

Abstract: An improved level shift circuit and method for level shifting is disclosed herein. In general, the improved level shift circuit adds a pulse generator, a feedback transistor and a latch to a conventional cross-coupled level shift circuit configuration. The pulse generator and feedback transistor are configured for reducing a fall delay associated with the level shift circuit. For example, the pulse generator is coupled for supplying a short duration feedback pulse to the feedback transistor during a first time period when input and output signals of the level shift circuit transition to a LOW state. The feedback pulse reduces the fall delay by increasing the speed with which the output signal is pulled LOW. The latch is coupled for preventing the feedback signal from floating when at least one of the input and output signals is HIGH. An integrated circuit comprising at least one level shift circuit is also contemplated herein.

Abstract: A dual processor framer includes a receiver and a transmitter which share common circuitry and/or code. Separate direct memory access controllers may be used for each of the receiver and transmitter. Processing is distributed over two or more processors. One processor may be a lower power processor while another processor may be a higher power processor. At least one of the two or more processors may be programmable or reconfigurable. The transceiver is configured to provide internal loop back self testing at various points in the processing. Timing within the transceiver may be established almost entirely by a single clock domain.

Abstract: An output stage circuit may include a sourcing driver device, a nonlinear local feedback loop having a feedback transistor and a first current mirror, a sinking driver device, and an output signal. The output stage circuit may actively and dynamically adjust the transconductance of the sourcing driver device by sensing its region of operation, and by sending a nonlinear feedback signal through the local feedback loop and the first current mirror. The nonlinear local feedback loop may be used for control and headroom compensation of the sourcing driver transistor to provide low distortion operation using a smaller size driver transistor.

Abstract: An optical scanning system in which plural scan lines are sequentially scanned, and parameters association with the scanning are monitored. If one or more parameters change during the scanning operation, the system automatically begins rescanning, rather than continuing to scan the entire frame. This results in a system that operates more quickly than prior art systems, which have to waste an entire frame.

Abstract: A voltage level translation circuit includes a first power supply voltage, a second power supply voltage, wherein the second supply voltage is lower than the first supply voltage, a low voltage input, wherein the low voltage input is referenced from the second supply voltage, a resistive element leaker transistor having a source and a drain, wherein the source is coupled to the first power supply voltage, a PMOSFET having a gate and a source, wherein the source is coupled to the first power supply voltage, and a pulse generator coupled to the gate of the PMOSFET, wherein the pulse generator is capable of controlling the operation of the PMOSFET.

Abstract: A halt control gatekeeper for an In-Circuit Emulation system. Halt commands are implemented through a gatekeeper forming a portion of a virtual microcontroller that operates in lock-step synchronization with a real microcontroller under test. When a halt command is received, the gatekeeper determines if the microcontroller is in a sleep mode and, if so, appropriately notifies a host computer and queues up a halt command. If the microcontroller is not in a sleep mode, the gatekeeper simply queues a halt command and notifies the host computer when the microcontroller has halted and it is safe to perform debug operations on the virtual microcontroller.

Abstract: In one embodiment of the present invention, a phase generator, comprising a plurality of delay blocks, is coupled in a feedback loop with a phase detector. When in an open loop mode, the phase generator is operable as a voltage controlled delay line. The phase detector compares an input signal with a first output signal of the phase generator and generates a first control signal based thereon. The phase generator is also coupled in a feedback loop with a phase-frequency detector. When in a closed loop mode, the phase generator is operable as a voltage controlled oscillator and the phase-frequency detector compares the input signal with a second output signal of the phase generator. The phase-frequency detector then generates a second control signal based thereon.

Abstract: The present invention is a method and apparatus for providing a pseudo random sequence for a spread spectrum system that prevents interception and provides real estate and power consumption efficiency. A pseudo random sequence may be created in real-time by associating a pseudo random sequence of a channel location of the carrier frequency at an instant in time. For example, the entire band of the spread spectrum system may be scanned to detect a channel with a low received signal strength. The location of the channel, or the actual frequency of the channel, could be associated with a particular pseudo random sequence to create a hop set for frequency hopping. Additionally, the location of a characteristic of the spread spectrum system, such as a noise characteristic, could be utilized to determine a content of a pseudo random sequence.

Abstract: An event architecture. The event architecture may have a number of event engines for monitoring conditions and also chain logic coupled to the event engines. The event architecture may further have a memory array for storing data to configure the chain logic to configure an execution scheme of the event engines. The chain logic may be re-configured by additional data from the memory to re-configure the execution scheme of the event engines.

Abstract: A method of making a semiconductor structure, comprises etching a nitride layer with a plasma to form a patterned nitride layer. The nitride layer is on a semiconductor substrate, a photoresist layer is on the nitride layer, and the plasma is prepared from a gas mixture comprising CF4 and CHF3 at a pressure of at least 10 mTorr.

Abstract: A mass storage device motherboard or secondary board includes a bridging circuit. The bridging circuit converts signals from the mass storage device into USB signals. The bridging circuit can be provided by a chip that converts ATA/ATAPI signals into USB signals.

Abstract: An embodiment of a method of evaluating costs and/or benefits of possible configurations of a manufactured product (e.g., an integrated circuit, an electronic system, etc.) includes establishing an upgrade cost and a redesign cost for each characteristic within a set of characteristics associated with the product configuration. The upgrade cost is the cost to upgrade the characteristic in a manner commensurate with other upgraded characteristics, while the redesign cost is the cost to redesign the product to accommodate the characteristic if it is not upgraded commensurately. A predicted total cost and a predicted benefit for a configuration may also be computed. In addition, the total cost for the corresponding configuration may be subtracted from such a benefit to determine a net benefit for the configuration. The method may be implemented using a computer-based system including upgrade cost data and redesign cost data.