Abstract: Systems and methods of flyback capacitor level shifter feedback regulation for negative pumps. In accordance with a first embodiment of the present invention, a feedback regulator for a negative output charge pump comprises a flyback capacitor for inverting an output of the negative output charge pump to a positive voltage. The feedback regulator further comprises a voltage comparator for comparing the positive voltage to a reference voltage. The voltage comparator is also for producing an enable signal for control of pump driving signals to the negative output charge pump. The feedback regulator further comprises a first plurality of switches for selectively coupling a first terminal of the flyback capacitor between a low voltage and the output and a second plurality of switches for selectively coupling a second terminal of the flyback capacitor between a low voltage and the voltage comparator. Further, the feedback regulator comprises switch control logic for controlling the plurality of switches.

Abstract: A switch circuit, system, and method are provided in which a single, shared data line is formed across the majority of the monolithic substrate which bears the switch. The shared data line is serviced by multiplexers and corresponding state machines placed near the ports of the switch. The state machine determines which one of a plurality of data streams received on the corresponding ports are to be serviced and placed in a first timeslot of multiple timeslots sent across the shared data path. A multiplexer select input responds to the state machine output by forwarding the selected data stream for a duration set by a timer within the state machine. An arbiter within the corresponding state machine determines which port is to served first and which data is to be placed in the first timeslot, but also can prioritize based on user-defined rules.

Abstract: A data interface is provided that can de-skew data signals by taking into account different skewing effects on each data signal. The data interface can be used, for example, in a communication system and can be configured to operate in one of three possible modes of operation. In the first mode, de-skewing is fixed prior to the sample logic. In the second mode, de-skewing is periodically changed automatically as the amount of skew changes based on training signals that are periodically sent into the data interface. The combination of the data phase count and the positive and negative clock width pulse counts will then determine where the final transition or edge of each data signal is to be placed within a bit. The third mode of operation involves an override or programmatic modification of the second mode of operation based on values stored in a register.

Abstract: An oscillator amplifier circuit is provided. The amplifier circuit can be used with a resonator to amplify and form a resonating oscillator. The amplifier circuit comprises an active circuit which includes an inverter and a current-controlled biasing circuit. One transistor of the inverter receives a voltage produced from the biasing circuit in order to place a gate terminal of that transistor at approximately a threshold voltage. The other transistor can be biased using a passive circuit element, such as a resistor. Therefore, both transistors are biased independent of each other within the optimal gain region. Large shunt capacitors are not required and the total current consumption is controlled through a variable resistor coupled to the source terminal of either the first transistor, second transistor, or possibly both transistors of the inverter to adjust the amplitude of the oscillating output.

Abstract: A method and apparatus for performing byte rate adaptation. Specifically, embodiments of the present invention describe a method for deleting bytes when performing byte rate adaptation. The method begins by receiving data at a first rate. The data comprises valid data and deletable data. The data also comprises a plurality of cycles, wherein each cycle comprises a word length of W bytes. The method continues by compressing the plurality of cycles into a compressed cycle by deleting redundant deletable bytes. The compressed cycle comprises at least one valid data byte. Thereafter, the method substitutes remaining deletable bytes in the first compressed cycle with a uniform character, and sends the compressed cycle to a FIFO buffer for further transmission.

Abstract: A semiconductor device memory cell (100) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell (100) can include a first inverter (102) and second inverter (104) arranged in a cross-coupled configuration. A capacitor (110) can be coupled between a first storage node (106) and second storage node (108). A capacitor (110) can be a “built-in” capacitor formed with interconnect wirings utilized to connect memory cell circuit components.

Abstract: A method and apparatus for creating USB peripheral device report descriptors: A short, compressed, report descriptor is stored in a peripheral device. This short report descriptor is transmitted to a USB wireless bridge and combined with templates stored in the bridge to create a USP report descriptor. Power is saved because less time is required to transmit the short report descriptor than would be required to transmit a full USB report descriptor. Hardware is also saved in the peripheral device since less memory is required to store the short report descriptors as compared to storing a full USB report descriptor.

Abstract: A method of removing a defect from a gate stack on a substrate, comprises treating the gate stack with a plasma. The plasma comprises fluorine, the gate stack comprises a gate layer and a metallic layer, and substantially no photoresist is present on the substrate.

Abstract: A method for arranging a semiconductor wafer within a photolithography tool and methods for processing a semiconductor wafer employing such an arrangement process are provided. The arrangement process includes positioning a semiconductor wafer on a stage in a pre-alignment unit of a photolithography tool such that a crystal orientation marker of the wafer is located at a first radial position. Thereafter, the wafer is moved to an exposure unit of the photolithography tool. During one or both of such steps, the semiconductor wafer is rotated such that the crystal orientation marker is relocated to a second, distinct radial position prior to arranging the wafer upon a stage of the exposure unit. In particular, the semiconductor wafer is rotated greater than approximately 10° and less than approximately 170° relative to the first radial position. The arrangement process is performed for lithography processes conducted during fabrication of a semiconductor device.

Abstract: Circuits, systems, and methods for fine tuning crystal frequency accuracy are disclosed. One such circuit fine tunes crystal frequency accuracy with a tunable fractional capacitance. The circuit includes an effectively constant capacitance coupled, e.g., fixedly, with the crystal. A second capacitance is controllably coupleable with the crystal. A switching device is controllable for switchably coupling the second capacitance with the crystal. An effective capacitance value associated with the second capacitance varies according to a time associated with that switchable coupling. The crystal resonating frequency changes according to a capacitive loading thereof, which includes the first capacitance and the effective capacitance value of the second capacitance, effectively time multiplexed therewith.

Abstract: A low voltage detect circuit is provided herein for detecting when an external voltage (Vext) drops below a predetermined minimum voltage. In general, the low voltage detect circuit described herein may be configured to detect a low voltage condition based on a threshold voltage difference between a non-zero threshold transistor having a substantially non-zero threshold voltage, and a zero threshold transistor having a threshold voltage relatively close to zero. According to a particularly advantageous aspect of the invention, the low voltage detect circuit described herein comprises substantially no resistors or reference voltage generation circuits, and therefore, provides significant savings in both current and die area consumption without sacrificing accuracy. The low voltage detect circuit of the present invention is particularly useful in power regulators, such as those used in memory systems or devices.

Abstract: An apparatus and a method for improving production yield of phase locked loops (PLLs) have been disclosed. One embodiment of the apparatus includes a PLL comprising a charge pump and an offset compensation circuit coupled to the charge pump to provide an offset current to the charge pump to reduce a static phase error of the PLL caused by a mismatch in at least one of a process variation, a voltage, and a temperature. Other embodiments are described and claimed.

Abstract: A wordline driver circuit can include single stage level shifters to translate a low voltage level (VGND to Vcc) to a high voltage level (Vnwl to Vpp). A wordline driver can further include a two-stage discharge circuit to pull down a wordline from a boosted high voltage Vpp to a boosted low voltage Vnwl. A two-stage discharge circuit can include (i) a first discharge path that can pull the wordline toward a first low voltage VGND; and (ii) a second discharge path that can pull the wordline toward a lower boosted low voltage Vnwl. Initially discharging a wordline to a first low voltage can reduce the amount of charge injected into a boosted low voltage Vnwl supply. A two-stage discharge circuit can be self timed or externally timed.

Abstract: An apparatus, computer program, and method are disclosed for generating computer executable code. The code is compiled from a data set, and the data set is compiled by selecting a link within a comments portion of a text editor portion of a program. The data set can then be inserted into an applications program to form the computer executable code. The comments portion involves a line of text that is preceded by a comments designator and succeeded by at least one link word that is adapted for modification by an on-screen pointer. Any changes to the link word via a graphical user interface will correspondingly change fields within a data set, which preferably is also displayed within the same window as the comments portion. The fields of bits within the data set can be used to program a hardware device or system. One example of such a device is a programmable device, or general purpose interface circuit that is juxtaposed between, for example, a computer and a peripheral device.

Abstract: Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a LUN processor that translates different LUN numbers received from the bus into different addresses and LUNs for devices connected to the bridge. The bridge masks the fact that multiple MSC devices are coupled to it by reporting to the host that only a single device having multiple LUNs are coupled to the bridge.

Abstract: Built-in self-test (BIST) devices and methods are disclosed. A BIST section (100) according to one embodiment can include a built-in seed value memory (150) that stores multiple seed values. In a BIST operation, a seed value can be transferred from a built-in seed memory (150) to a test pattern generator (106) to generate multiple test patterns for scan chains (104-0 to 104-n). Successive seed values can be transferred to generate multiple test patterns sets at a clock speed and/or to achieve a desired test coverage.

Abstract: A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second count value CNT2 according to a second clock signal CLK2. First separation-detect logic (102-0) and second separation-detect logic (102-1) determine if a pre-specified difference exists between a first count value (CNT1/CNT1?) and second count value (CNT2/CNT2?). According to such determinations, separation information (INF—1 and INF—2) can be generated indicating which clock signal (CLK1 or CLK2) is faster. Selection logic (106) can select a faster of the clock signals (CLK1 or CLK2) if the separation information values confirm one another.

Abstract: A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.

Abstract: A method and device for supplementing current from the USB bus for enumerating USB devices that require additional current beyond that allowable by USB bus specification. A chargeable power source, such as a capacitor or rechargeable battery, is supplied to the enumeration circuitry and is charged from the USB bus for an initial period of time. The charged power source is then discharged to supplement the allowable current available for enumeration during a second period of time. It is during this second period of time that the enumeration takes place. The circuitry may exist in the USB device or may be supplied separately as a power monitor or power maintenance chip or device.

Abstract: A programmable latch circuit (100) can include a programmable data circuit (104) with a data load path (116) that can enable a data value to be recalled into a volatile latch (102). A data load path (116) can be formed with devices (P100-P102) having low threshold voltages. Data can be loaded via data load path at lower power supply voltages levels, such as on power-on and/or reset operations. Other embodiments disclose, self-test circuits, full redundancy capabilities, and resistors for limiting current draw in an anti-fuse program operation.