Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.

Abstract: A method and apparatus for creating USB peripheral device report descriptors: A short, compressed, report descriptor is stored in a peripheral device. This short report descriptor is transmitted to a USB wireless bridge and combined with templates stored in the bridge to create a USP report descriptor. Power is saved because less time is required to transmit the short report descriptor than would be required to transmit a full USB report descriptor. Hardware is also saved in the peripheral device since less memory is required to store the short report descriptors as compared to storing a full USB report descriptor.

Abstract: A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the ground supply, and a second pair of transistors, which is coupled to the first pair of transistors for controlling a current passed there through. In general, the second pair of transistors may be configured for increasing the amount of current passed through the first pair of transistors. For example, the second pair of transistors may utilize a bootstrapping effect to increase a pair of control voltages supplied to the gate terminals of the first pair of transistors. The increased control voltages function to over-drive the gate terminals of the first pair of transistors, thereby increasing the amount of current passed there through.

Abstract: An arbiter circuit (100) can include a latch circuit (102) that latches competing input signals (MATCH1 and MATCH2) to generate signals on latch output (110-0 and 110-1). A filter section (104) can prevent metastable states of latch output signals from propagating through to output signals (BUSY2 and BUSY1). In addition, filter section (104) can generate output signals (BUSY2 and BUSY1) having one set of values when both inputs are inactive, and a second set of values when latch (102) is in the metastable state.

Abstract: Embodiments of a method and apparatus for aggregating Ethernet streams are generally described. According to but one example embodiment, implementations of a physical coding sublayer (PCS) modify one or more Ethernet streams to uniquely distinguish at least one of the Ethernet streams from the other Ethernet streams. Any two or more of the modified Ethernet streams may be interleaved to form an aggregate Ethernet stream. The aggregate Ethernet stream may by transmitted over a serial link.

Abstract: A method for emulating and debugging a microcontroller. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information are effectively pre-filtered. Accordingly, it is not incumbent on a designer to read and understand the event and trace information and sort out the information that is of interest. Instead, this task is essentially done automatically, helping the designer and reducing the probability of error. Furthermore, because only selected event and trace information is recorded, the resources of the in-circuit emulator system are not taxed.

Abstract: Memory circuits having different configurations of local word line driving circuits (LWLDC) and methods for designing such circuits are provided. The memory circuits include an array of memory cells and a plurality of local word lines each coupled to a different subset of the array of memory cells. The memory circuit further includes a plurality of LWLDC respectively coupled to the plurality of local word lines, a global word line bus coupled to the plurality of LWLDC, and a global word line driving circuit (GWLDC) coupled to the global word line bus. At least one of the plurality of LWLDC may be configured to have a smaller amount of load capacitance than another LWLDC arranged comparatively farther from the GWLDC. In some embodiments, the variance of load capacitance may be induced by a variance of size among the plurality of LWLDC, specifically with reference to different transistor width dimensions.

Abstract: Disclosed is an apparatus and method for an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments. The apparatus may include a data extraction block, a plurality of data assemblers, a scheduler, and an output memory. The scheduler may be configured to operate according to a scheduling policy. The scheduling policy may include a set of priorities to determine an order of scheduling writes to the output memory from a plurality of data assemblers.

Abstract: A capacitive sensing system (100) can connect groups of capacitive sensors (112-1 to 112-N) to a common node (106) to detect change in capacitance. States of a set of capacitive sensors (112-1 to 112-N) can thus be scanned faster than approaches that scan such sensors one-by-one. Faster scanning can allow for reduced power consumption in applications that only periodically scan the set of capacitive sensors (112-1 to 112-N).

Abstract: A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.

Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

Abstract: A reference circuit can include a reference section that provides a reference value for other circuits of an integrated circuit and can be enabled and disabled in response to an enable signal. The reference circuit can include at least a first node, draw a reference current in the enabled mode, and draw essentially no current in the disabled mode. A pulse start-up section can provides a low impedance path between the first node and a first potential for a predetermined duration in response to the reference circuit being enabled. A continuous start-up section can provide a low impedance path between the first node and the first potential based on a logic state of an enable signal.

Abstract: An apparatus for an improved Ball Grid Array (BGA) package includes a semiconductor device having a radio frequency (RF) input or output, an antenna pad, and a BGA package structured to house the semiconductor device and the antenna pad. The antenna pad may be coupled to the radio frequency (RF) input or output, and the antenna pad is structured to reduce the inductance of the BGA package. The antenna pad may include a pad disposed above the semiconductor device, a pad disposed to the side of the semiconductor device, or an antenna chip. An antenna may be coupled to the antenna pad. The antenna may include a trace antenna, a staggered antenna, or a helical antenna.

Abstract: A semiconductor imager structure having a well region formed in a substrate layer. The well region being of a predetermined shape having a plurality of corners being non-right angles.

Abstract: Circuits and methods are provided herein for monitoring the integrity of a power supply, the circuits and methods providing additional resources/information for diagnosing a cause behind a reset signal, and in some cases, a reason behind a power failure. A first method described herein provides exemplary steps for monitoring a level of a power supply voltage supplied to one or more system components. A second method describes exemplary steps for monitoring an electrical connection between the power supply (or ground supply) and one or more supply pins. Each of the methods involves monitoring a state of one or more bits stored, e.g., within a status register. The methods may be used separately, or in conjunction with one another, for detecting the occurrence of a power abnormality.

Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dielectric thickness of less than approximately 20 angstroms.

Abstract: Embodiments of a high-speed level shifter are described. The level shifter may include a first transistor having a drain, a source, and a gate and a second transistor having a drain, a source, and a gate. The first and second transistors may be operable to receive a pair of differential signals. The level shifter may further include a third transistor having a drain, a source, and a gate, the drain of the third transistor directly coupled to the source of the first transistor, and the source of the third transistor directly coupled to the source of the second transistor. The gate of the third transistor is driven by a level-shifted version of an output voltage generated from the pair of differential signals.

Abstract: A method of forming a polished semiconductor structure comprises polishing a surface of a semiconductor structure by chemical mechanical polishing. Pressure applied to the surface is reduced during the polishing, or a rotation rate of a polishing surface relative to the surface is reduced during the polishing.

Abstract: A method and circuit for performing switching in a frequency timing generator is described. The method includes detecting a request for a new value for a feedback counter or an reference counter, upon which a loading operation is synchronized for the appropriate counter. A time-out order of the feedback counter and the reference counter is determined. Where no time-out order difference is detected therein, a state machine status word function is completed. Where a time-out order difference is detected therein, it is determined which of the reference counter and the feedback counter times out first. Where the reference counter times out first, a constant charge pump current is delivered to a loop filter associated with a phase locked loop to achieve an upward frequency direction. Where the feedback counter times out first, a constant charge pump current is delivered to the loop filter to achieve a downward frequency direction.

Abstract: Systems and methods of flyback capacitor level shifter feedback regulation for negative pumps. In accordance with a first embodiment of the present invention, a feedback regulator for a negative output charge pump comprises a flyback capacitor for inverting an output of the negative output charge pump to a positive voltage. The feedback regulator further comprises a voltage comparator for comparing the positive voltage to a reference voltage. The voltage comparator is also for producing an enable signal for control of pump driving signals to the negative output charge pump. The feedback regulator further comprises a first plurality of switches for selectively coupling a first terminal of the flyback capacitor between a low voltage and the output and a second plurality of switches for selectively coupling a second terminal of the flyback capacitor between a low voltage and the voltage comparator. Further, the feedback regulator comprises switch control logic for controlling the plurality of switches.