Abstract: The present invention is directed to a content player that allows a user to access media content through an information appliance. The content player is suitable for receiving media content from a network, then the media content may be transmitted to various information appliances. The information appliance is suitable for receiving the media content from the content player and conveying the media content. The information appliance, itself, may be capable of controlling the media content transmitted from the content player and received by the information appliance.

Abstract: A method of forming a semiconductor structure comprises oxidizing a stack, to form sidewall oxide in contact with sides of the stack. The stack is on a semiconductor substrate, the stack includes a gate layer, comprising silicon; a metallic layer, on the gate layer; and an etch-stop layer, on the metallic layer. The sidewall oxide in contact with the metallic layer is thinner than the sidewall oxide in contact with the gate layer.

Abstract: An input buffer circuit and associated method operable in a normal mode and a hot-plug mode. In one example, the input buffer has an input and a buffer output, and the input buffer may include a pull-up path coupled between a first circuit supply and the buffer output; a pull-down path coupled between the buffer output and a ground reference voltage; a first transistor coupled between the input and the pull-up path to activate the pull-up path; a second transistor coupled between the input and the pull-down path to activate the pull-down path; and a third transistor for protecting the pull-up path from over-voltage. The input buffer circuit may be configured to prevent an over-voltage condition on each of the plurality of transistors and the input buffer circuit may be configured to allow a hot-plug operation.

Abstract: A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three distinct power domains. In other words, the logic gate inputs may be further isolated by gating each signal in its own power domain. In addition, the multiplexer circuit provides built in delay matching by utilizing three substantially identical logic gates.

Abstract: A method for obtaining real-time debug information, e.g., state information and trace information, from an FPGA acting as a virtual microcontroller that is attached to a microcontroller under test. The two devices, the microcontroller and the FPGA execute the same instructions in lock-step with the FPGA acting as an emulator. The FPGA emulates the actual microcontroller and relieves the actual microcontroller from having debug logic installed thereon. FPGA and microcontroller, are coupled using a four pin interface. The FPGA is directly coupled to the PC for both programming and control. The system is implemented such that the microcontroller forwards information regarding I/O reads, interrupt vector information and watchdog information to the FPGA in time before the execution of the next instruction. Thus, the FPGA has an exact copy of the state information of the microcontroller.

Abstract: An analog spread spectrum signal generation circuit. A clock generator generates a periodic signal. A plurality of switchable analog loading elements each load the periodic signal by a respective load to vary propagation delay of the periodic signal to an output node. A decoder controls the plurality of switchable analog loading elements. A counter coupled to drive the decoder causes the output node to generate a periodic spread spectrum signal with modulated phase. In one embodiment, the periodic spread spectrum signal with modulated phase is used for reducing radiated electromagnetic interference and downstream phase-locked loop tracking error.

Abstract: Circuits and methods for controlling the amplitude of oscillation of a crystal. In one example, a circuit may include a peak detector; a first voltage-to-current converter; a first current-to-voltage converter coupled with the first voltage-to-current converter; a second voltage-to-current converter; a second current-to-voltage converter coupled with the second voltage-to-current converter; and a differential amplifier; wherein a ratio between a size of first voltage-to-current converter and a size of the second voltage-to-current converter is used to control the gain of the circuit.

Abstract: Systems and method for tracking different types of transconductance cells is shown and described. In these multi-cell systems, the addition of one or more tracking control modules allows circuit designers to advantageously incorporate multiple transconductor topologies and their uniquely beneficial characteristics into their designs, without eradicating its centralized multi-cell tuning functionality.

Abstract: A system and method comprising a non-volatile memory including one or more memory blocks to store data, a controller to allocate one or more of the memory blocks to store data, and a wear-leveling table populated with pointers to unallocated memory blocks in the non-volatile memory, the controller to identify one or more pointers in the wear-leveling table and to allocate the unallocated memory blocks associated with the identified pointers for the storage of data.

Abstract: A memory device, apparatus and method are provided for accessing memory cells. The device, apparatus, and method allow two or more electronic subsystems with corresponding external ports to access a single array of memory elements via a single internal port. Address, data, and control signals from each of the external ports are multiplexed onto the word line drivers and de-multiplexed from the sense amplifiers. Multiplexing and de-multiplexing operations are sequenced based on a state machine that receives synchronized signals from the external port. The synchronized signal can be clock signals that are synchronized to a high-speed sampling clock. Synchronization and sequencing functions can occur over a relatively few number of cycles of the high-speed sampling clock to minimize the time for resolving access conflicts, thereby maximizing the number of external ports which can access the internal port of the array.

Abstract: A method and apparatus for programming nonvolatile (flash) memory in a microcontroller. A nonvolatile memory in the microcontroller is connected via data, address and control signal paths to a processor internal to the microcontroller. These paths are not available to the outside world. In order to program the nonvolatile memory, a tester/programmer provides instructions to a test/control interface and the actual programming of the nonvolatile memory is carried out under control of a supervisory ROM forming a part of the microcontroller storing instructions which are carried out by the processor.

Abstract: Embodiments of the present invention effectuate a method and system for debugging a device such as a microcontroller in a distributed architectural scheme, where the device may operate at speeds much faster than the debugger program is run, with limited debugging resources physically incorporated into the device itself, and with relatively limited computational capacity, vis-à-vis the platform deploying the debugging software. The embodiments place relatively modest, uncomplicated demands on the debugger software, and the ICE may also be relatively simple. Further, debugging methods and systems according to these embodiments are flexible and adaptable to a variety of different devices that must undergo debugging, yet remain effective, simple, and inexpensive.

Abstract: A dual damascene interconnect structure, produced using etch chemistry based on C2H2F4, includes (i) an etch stop layer of either undoped silicon oxide or doped silicon oxide, and (ii) dielectric layers both above and below the etch stop layer of the other (i.e., when the etch stop layer comprises undoped silicon oxide, the dielectric layers above and below the etch stop layer independently comprise a doped silicon oxide; and when the etch stop layer comprises doped silicon oxide, the dielectric layers above and below the etch stop layer independently comprise an undoped silicon oxide).

Abstract: A charge pump circuit with resistively attenuated inputs is described herein. By reducing a voltage swing of input signals supplied thereto, the charge pump circuit described herein is configured for producing output signals with relatively low static phase offset even when operating at relatively low power supply voltages (e.g., less than about 1.2 volts). In general, the input voltage swing may be reduced by coupling an attenuator to each input of the charge pump circuit. A method for operating the differential charge pump is described, along with exemplary devices (e.g., PLL and DLL devices) within which the charge pump may be utilized.

Abstract: A USB to PCI bridge preferably includes a USB interface, a PCI interface, and an on-board processor configured to manage data flow between the interfaces. Firmware is preferably provided and configured to translate signals between the USB and PCI interfaces. The bridge can also include an internal memory configured to store instructions and data. A PCI central resource can be provided to enable hosting of a PCI subsystem. In a preferred embodiment, a plurality of PCI targets can be connected to a USB port through the bridge.

Abstract: A circuit (100) can include a first section (102) that can provide a designated function within an integrated circuit device that can be altered due to current injection at a node (106). A mirror section (104) can mirror the effects of current injection on one or more devices within first section (102) and generate an output indication INJ_EFF representing such effects. In one very particular arrangement, detection of an injected current can be used to prevent false triggering of a switched electrostatic discharge (ESD) current path.

Abstract: A photodiode sensor structure includes a first dopant type substrate with a first surface and a second dopant type well region with a second surface. The second dopant type well region is formed in the first dopant type substrate such that the first surface and the second surface are substantially co-planar to form a diode surface. An interface between the second dopant type well region and the first dopant type substrate at the diode surface forms a diode junction. A poly silicon region is formed along the periphery of the entire diode junction. The poly silicon region provides the p-n junction of the photodiode with a physical shield to prevent any process damage from being introduced after the poly silicon processing (including damages from processes such as dielectric deposition/pattern, metal deposition/pattern, and/or via/contact hole etching), thereby reducing leakage current.

Abstract: A frequency doubler circuit with trimmable current control. In one embodiment, the present invention provides a circuit comprising an oscillator with a current source and a frequency doubler circuit coupled to the current source. In one embodiment, the current source is for generating a reference current. In one embodiment, the frequency doubler circuit is operable to receive a first frequency signal for generating a second frequency signal and also receiving the reference current. The frequency doubler circuit, using the reference current, operates to compensate for process variation of capacitance of the frequency doubler circuit and uses the reference current to maintain a known duty cycle.

Abstract: A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.

Abstract: Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be translated using the disclosed circuit. The biasing circuit can be formed using either inverters or transmission gates. Moreover, the biasing circuit, the inverter chain stage, and the amplifier stage can be connected to a power down circuit which, when the translator is not being used, will ensure various circuitry of the translator will not consume extensive power. The inverter chain stage, biasing circuit, and capacitor stage are formed on both an upper and lower section to produce true and complementary outputs that have a consistent and equal delay from the transitions of the incoming differential input signal so as to minimize jitter and associated duty cycle of the translated output.