Abstract: A method is provided for processing a semiconductor topography such that its upper surface is substantially planar, particularly including a region adjacent to an outer edge of a semiconductor topography. The method may include preferentially removing a portion of an upper layer of the topography in a region adjacent to an outer edge of the semiconductor topography. The region may extend greater than approximately 3 mm inward from the outer edge of the semiconductor topography. The method may also include polishing the semiconductor topography such that the upper surface of the semiconductor topography is substantially planar. Therefore, although a rate of polishing adjacent to an outer edge of the semiconductor topography may be slower than a rate of polishing adjacent to a center of the semiconductor topography, a thickness variation of the polished upper layer across the entirety of the semiconductor topography may be less than approximately 500 angstroms.

Abstract: An improved key matrix scanning technique conducts a first pre-scan on a first array of connections in a key matrix to identify any activated keys or buttons associated with the first array. A second sub-scan is conducted on a second array of connections in the key matrix but only for the connections in the first array that are detected as having activated keys.

Abstract: The invention relates to an automatic documentation tool and associated method. The method includes embedding comments into a plurality of source files defining the design, creating a configuration file including parameters associated with each source file, and extracting the comments from each source file responsive to the parameters. The method is capable of operating on a plurality of source files originating from a plurality of design tools. The method is capable of sorting through keywords preceding each comment and ordering the comments according to a user's request. The method is capable of receiving register definitions from a header file.

Abstract: The present invention is a method and apparatus for optimizing performance of a transceiver selecting and processing an intermediate frequency free of significant interference, such as noise. A frequency band may be scanned to detect interference upon which an intermediate frequency free of significant interference may be selected. This may enhance performance of the receiver by reducing the effects of noise. Additionally, perrformance may be further optimized by adjusting the passband of the filter such that the center of the passband matches the selected intermediate frequency. This may provide stability as centering of the passband may account for process, voltage and temperature variations and errors. Further, performance may be enhanced by ensuring desirable signal attributes are passed through the filter.

Abstract: A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an address signal to an address input of a multiplexer, to transmit a data signal to a data input of the multiplexer, and to transmit a control signal to a control input of the multiplexer. The control signals may include burst type control signals. The multiplexer is capable of selectively coupling a selected master device chosen from the group consisting of the master devices to a bus. The bus architecture further includes an arbiter arranged to receive the bus request signals as first inputs and arranged to receive the burst type control signals as second inputs, where the burst type control signals are received from an ingress side of the multiplexer.

Abstract: In one embodiment, an image sensor for an x-ray imager includes a photodiode and a readout circuit. A deep well formed below the readout circuit may be configured as a diode to drain away parasitic electrons, which would otherwise induce noise in images. The parasitic electrons may be drained away to a power supply or a measuring circuit for dosimetrie purposes, for example.

Abstract: A method and an apparatus to bias a charge pump in a phase locked loop (PLL) to compensate a voltage controlled oscillator (VCO) gain have been disclosed. One embodiment of the apparatus includes a PLL comprising a charge pump, the charge pump comprising an input and an output, and a bias circuit coupled to the input of the charge pump, the bias circuit comprising a sensor circuit to sense a temperature and at least one of a voltage and a process variation and a current reference circuit coupled to the sensor circuit.

Abstract: A method of forming a semiconductor structure comprises forming sidewall oxide on a stack, by rapid thermal oxidation. The stack is on a substrate and comprises (i) a first layer comprising silicon, (ii) a second layer, comprising silicon and tungsten, on the first layer, and (iii) a capping layer, on the second layer. The sidewall oxide in contact with the second layer is at most 50% thicker than the sidewall oxide in contact with the first layer.

Abstract: One embodiment in accordance with the invention is a circuit. For example, the circuit can include a first stage amplifier coupled to receive a reference voltage. The circuit can also include a second stage amplifier coupled with an output of the circuit and the first stage amplifier. Note that the output can be fed back to the first stage amplifier. Additionally, the circuit can include a module coupled with the second stage amplifier and can restrict current flow to the second stage amplifier and the output provided the circuit is in a sleep mode. Furthermore, the module can drive a terminal of the second stage amplifier to a logic low voltage provided the circuit is in the sleep mode.

Abstract: A microcontroller includes a wide band, high gain amplifier on-chip capable of driving a 32 ohm speaker. The amplifier is controllable by the microcontroller processor to either enable or disable the amplifier and switch between multiple modes of power. In one embodiment, one or more such amplifiers are situated anywhere on the integrated circuit die including at the corners of the die.

Abstract: Programming a plurality of states having respective threads is achieved by an event engine and a computer controlled GUI causing the event engine to monitor a signal and execute an action based thereon. The GUI programs an event and several states and causes the event engine to traverse between the states upon reaching the event. The GUI further programs a logic chain which unifies the threads. A method unifies several threads by selecting and executing a logic operation. The method further configures several states and causes traversing between them. The GUI may be deployed co-functionally with debuggers, logic analyzers, scopes, utilities, and software development tools. The results of the GUI are automatically transformed into program code which programs the event engine to operate during debug of a device under test by monitoring for events and taking action based thereon.

Abstract: A latching circuit is provided that includes a latch, a storage element, and a selection circuit coupled between the latch and the storage element. The latch can receive true and complementary voltage values from, for example, a data bus and, if called upon, forward the latched value to the non-volatile storage element via the selection circuit. Control signals sent to the selection circuit allow the latched data to be written to or read from the storage element. Once programmed, the voltage values will remain in the latching circuit even after power is removed. If the latched data is not sent to the non-volatile storage element, the latching circuit essentially functions as a volatile latch, and the data will be lost if power is removed. The switching circuit thereby operates as a dual-purpose volatile and non-volatile latching circuit that can be embodied as an array of latching circuits that temporarily and/or permanently store true and complementary data signals.

Abstract: An improved USB to ATA bridge circuit that issues a speculative write command upon the completion of an actual write command: The speculative write command assumes that the next write command will write data in a the next sequential data location to that in which data was written by the preceding write command. When the next actual write command is received, the address to which data is to be written is compared to the address used by the speculative write command, if the addresses match, the data is written when the storage device is ready. If the addresses do not match the data transfer is started and immediately stopped.

Abstract: A method and device for handling the refresh requirements of a DRAM or 1-Transistor memory array such that the memory array is fully compatible with an SRAM cache under all internal and external access conditions. This includes full compatibility when sequential operations alternate between memory cells in same row and column locations within different memory banks. The device includes bi-directional buses to allow read and write operations to occur between memory banks and cache over the same bus. The refresh operations can be carried out without interference with external accesses under any conditions.

Abstract: Embodiments of the present invention relate to a method and mechanism for configuring input/output connections in a programmable logical device, which comprise presenting a graphical user interface enabled to aid in configuring the programmable logical device, selecting a configuration presentation from the graphical user interface, selecting an I/O pin to be configured from the configuration presentation and selecting options for configuring the pin from among those presented in a selection set presented by the graphical user interface. The pins to be configured can be selected from either a graphical presentation or a parameter table and option selection sets can be presented in pop-up windows or drop-down lists.

Abstract: A memory interface system and method are provided for transferring data between a memory controller and an array of storage elements. The storage elements are preferably SRAM elements, and the memory interface is preferably one having separate address bus paths and separate data bus paths. One address bus path is reserved for receiving read addresses and the other address bus path is reserved for receiving write addresses. One of the data bus paths is reserved for receiving read data from the array, and the other data bus path is reserved for receiving data written to the array. While bifurcating the address and data bus paths within the interface is transparent to the memory controller, the separate paths afford addressing phases of a read and write address operation to be partially overlapped, as well as the data transfer phases.

Abstract: A method for recovery from overstress conditions, comprising the steps of (A) detecting an overstress event, (B) storing an occurrence of the overstress event and (C) taking appropriate action in response to the stored occurrence of the overstress event.

Abstract: A system and method for bi-directional communication between a system controller and a fan controller: The system operates in two modes and there are two communication paths between the system controller and the fan controller. The first communication path provides a PWM signal the frequency of which indicates the mode in which the system is operating. During the first mode, the duty cycle of the PWM signal on the first signal path indicates the desired fan speed. In the first mode, the second communication path carries a conventional tachometer signal. In the second mode the second communication path operates as a bi-directional communications signal path between said system controller and said fan controller.

Abstract: A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respectively, a comparator, and a clock driver circuit. A linearly increasing (or ramped) voltage waveform is generated within the storage device by the charging and discharging actions of the charge and dump sub-circuits; a periodic process which is controlled by opposite phases of the input clock. By programming the DAC control input to change the slicing threshold of the ramped waveform, the circuit and method described herein provides a means for programmable phase shifting and duty cycle correction.

Abstract: Systems and methods for performing encoding and/or decoding can include an input data path that receives multiple input data values having an order (significance) with respect to one another. Each input data value can be applied to multiple compute paths (106-1 to 106-N), each of which can precompute multiple output values based on a different predetermined disparity value. Multiplexers (114-1 to 114-N) can output one precomputed output value according to a disparity value corresponding to a previous input data value in the order.