Abstract: An apparatus comprising a distributed multiplexer configured to receive a distributed input group of signals. The distributed multiplexer may be configured to evenly load the distributed input groups.

Abstract: A circuit, system, and method are provided for generating edge-aligned, complementary output signals from complementary input signals. The output and input signals can, according to one example, be clock signals. The circuit, system, and method can use the rising edges of the complementary pair of input signals to trigger transitions on the complementary pair of output signals. More specifically, the rising edge of a true input clock signal will trigger the rising edge of the true output clock signal and the falling edge of the inverted output clock signal. A rising edge of the inverted input clock signal will trigger the falling edge of the true output clock signal, and the rising edge of the inverted output clock signal. Moreover, the circuit, system, and method ensures that at any time only one transition occurs on the active inputs of a final logic stage of the clock generation circuit.

Abstract: A data path (200) can be configured to accommodate different clocking arrangements. In one mode, data values may be output at a single data rate: one data value every clock cycle. In another mode, data values may be output at a double data rate: two data values every clock cycle. A data path (200) can be compact circuit structure, needing only an additional mode multiplexer (206) and inverter over a conventional D-type master-slave flip-flop.

Abstract: A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port circuit may be configured to determine an identification value in response to the signal.

Abstract: A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an etched portion of the semiconductor topography. Such defects may include bilayer mounds of nitride and a material comprising silicon, for example. In some embodiments, the method may include etching a stack of layers within a single etch chamber. The stack of layers may include, for example, a nitride layer interposed between an anti-reflective layer and an underlying layer. In addition, the single etch chamber may be a plasma etch chamber designed to etch materials comprising silicon. As such, the method may include etching an anti-reflective layer in a plasma etch chamber designed to etch materials comprising silicon.

Abstract: The quality and reliability of electro-optical modules can be improved, for instance, through improved testing and burn-in of an electro-optical sub-assembly. Reliability can also be enhanced through better methods of constructing an electro-optical module. By arranging both an electrical interface and an optical interface on a sub-assembly, for instance, testing can be performed on both interfaces in a single testing process. Burning-in an electro-optical sub-assembly can also improve the reliability of the module by identifying defects. A method of forming an electro-optical module can provide improved reliability by testing and/or burning-in an electro-optical sub-assembly before assembling the module.

Abstract: A capacitive sensing system (200) can include a sense section (202) and a filter section (206). Sense section (202) can activate logic outputs based on a sensed capacitance from sensors (210-1 and 210-2). A filter section (206) can logically combine logic outputs in different ways to generate output signals (INT—1 and INT—2). According to output signals (INT—1 and INT—2), different types of movement in a capacitive body (212) can be detected.

Abstract: A system and method for using Extensible Markup Language (XML) as a scripting language to drive testing of a software program. XML is used to define a markup language in a script that provides commands that are interpreted by a test control processor. The test control processor includes an XML processor for processing the script. Using the script, the test control processor submits instructions to a software program and extracts the behavior of the software program. The software program behavior is tested by submitting multiple sets of instructions and comparing the results. Information regarding the software program behavior and test results is written to an output log file by the test control processor.

Abstract: A frequency synthesizer is provided having a fractional-N control circuit and method that can selectively apply any fractional ratio to a frequency divider within the feedback loop of a PLL. A special digital delta-sigma modulator can be implemented as the control circuit and can receive any arbitrary numerator and denominator value, or their arithmetic combination, or a positive and negative vector values used by the modulator to achieve an average fractional division. Both the numerator and denominator (or the positive and negative vectors) can be chosen based on any integer value to achieve a more optimal, higher frequency resolution and efficient fractional-N control circuit and methodology thereof.

Abstract: A sense amplifier, system and methods for increasing a noise margin of the sense amplifier are contemplated herein. In general, the sense amplifier includes a pair of cascode transistors coupled in parallel between a power supply node and a sense line of the sense amplifier. The sense amplifier also includes a precharge node coupled to the power supply node through a first precharge transistor, and a sense node coupled to the power supply node through a second precharge transistor. The sense amplifier described herein functions to separate the sense node from the precharge node with the pair of cascode transistors, which in turn, increases the noise margin of the sense amplifier by decoupling the sense node from any voltage fluctuations that may be present on the sense line during a sensing state.

Abstract: A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The apparatus may further include a second circuit coupled to the first circuit to drive the first circuit. The second circuit may comprise at least one of a latch and a feedback device.

Abstract: A method for entering test mode of an integrated circuit device is disclosed. In one embodiment of the present invention, after a lockout period, a test controller generates a signal indicating the integrated circuit is willing to enter the test mode. After the signal, the test controller monitors a test interface during a predetermined period of time for a digital password. Then, in response to a valid password being received within the predetermined period, the test controller enters the test mode. In another embodiment, in addition to the above steps, in response to the valid password being received, the test controller generates an acknowledge signal. In one embodiment, the predetermined period of time takes place during a holdoff period after the lockout period. In another embodiment, the test interface is serial.

Abstract: In one embodiment, a power on reset circuit includes a main circuit and a translation circuit. The main circuit may be configured to receive an external signal and to generate an input signal that is indicative of a state of the external signal. The translation circuit may be configured to receive the input signal and provide a power on reset signal indicative of a brownout condition of the external signal. The external signal may be a relatively high voltage signal compared to the power on reset signal.

Abstract: A method and an apparatus to detect low voltage have been disclosed. One embodiment of the apparatus includes a main circuit powered at a supply voltage, wherein the supply voltage changes over time and a test circuit coupled to the main circuit, the test circuit being representative of a voltage sensitivity of the main circuit to dynamically determine if the supply voltage is above a minimum voltage at which the main circuit operates correctly, wherein the minimum voltage changes over at least one of a temperature and a time and between different instances of the main circuit.

Abstract: The present invention adds an additional feedback loop to a phase locked loop (PLL). The additional feedback loop detects if the actual output frequency of the PLL is above or below the desired output frequency. If the actual output frequency is above the desired output frequency a signal is added to the forward path of the PLL to decrease the frequency of the PLL oscillator. If the actual output frequency is below the desired output frequency a signal is added to the forward path of the PLL to increase the frequency of the PLL oscillator.

Abstract: An oscillator circuit is provided that is preferably a crystal oscillator, where voltage placed across the crystal is regulated. The regulated voltage or amplitude of the cyclical signal across the crystal is monitored and maintained through a regulation circuit that measures a peak voltage across the crystal. Once the peak voltage exceeds a predetermined setpoint value, then a controller within the regulation circuit will reduce a biasing current through an amplifying transistor within the amplifier coupled across the crystal input and output nodes. By regulating the biasing current, gain from the amplifier is also regulated so that unwanted non-linearities and harmonic distortion is not induced within the crystal to cause frequency distortion and unwanted modes of oscillation within the crystal. The amplifier is preferably symmetrical in that the amplifier sources and sinks equal current to reduce unwanted peaks at the negative or positive half cycles of the sinusoidal signal.

Abstract: A method and system for a feed-forward encoder is described. The method includes evaluating one or more source characters to determine whether each source character will invert or maintain a current running disparity and determining a running disparity for each source character before encoding the source character based on the current running disparity and whether the source character will invert or maintain the current running disparity. The current running disparity along with the associated source character may then be passed to an encoder to encode the source character into a transmission character.

Abstract: A mask identification (ID) bit circuit (100) is disclosed that provides one of two potentials (VGND or VPWR) to a sense node (108). A mask ID bit circuit (100) may include a number of links (102-0 to 102-4) arranged in series. A link (102-0 to 102-4) may include inputs (104-0 and 104-1) and outputs (106-0 and 106-1). In one configuration, inputs (104-0 and 104-1) may be directly coupled to outputs (106-0 and 106-1). In another configuration, inputs (104-0 and 104-1) may be cross coupled to outputs (106-0 and 106-1). Cross coupling inputs (104-0 and 104-1) and outputs (106-0 and 106-1) of a link (102-0 to 102-4) can switch a potential (VGND or VPWR) supplied to a sense node (108). The configuration of more than one link (102-0 to 102-4) of a mask ID bit circuit (100) can be changed, allowing a sense node to be switched between two potential (VGND and VPWR) multiple times. According to an embodiment, n mask ID bit circuits (100) may provide as many as 2n different mask ID codes.

Abstract: A frequency synthesizer is provided having a fractional-N control circuit and method that can selectively apply any fractional ratio to a frequency divider within the feedback loop of a PLL. A special digital delta-sigma modulator can be implemented as the control circuit and can receive any arbitrary numerator and denominator value, or their arithmetic combination, or a positive and negative vector values used by the modulator to achieve an average fractional division. Both the numerator and denominator (or the positive and negative vectors) can be chosen based on any integer value to achieve a more optimal, higher frequency resolution and efficient fractional-N control circuit and methodology thereof.

Abstract: Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described. Elements of lower-threshold voltage NMOS devices are formed at first locations on a substrate. Elements of higher-threshold voltage PMOS devices are formed at second locations on the substrate. Elements of higher-threshold voltage NMOS devices and elements of lower-threshold PMOS devices are formed by adding a same amount of p-type dopant at selected locations chosen from the first and second locations.