Abstract: An apparatus comprising a flag generation circuit configured to generate a full flag signal in response to (i) a read clock signal, (ii) a write clock signal and (iii) a look ahead bitwise comparison configured to detect when a read count signal and a write count signal are equal.

Abstract: In one embodiment, an anti-wafer structure includes a silicon on insulator (SOI) layer and a plurality of probe dice formed on the SOI layer. Each of the probe die may have a pad layout corresponding to a pad layout of a die on a wafer under test. A plurality of holes may extend through the SOI layer and the plurality of probe dice, with each hole corresponding to a pad on a probe die. The anti-wafer structure may be advantageously used in an advanced probe card. Techniques for fabricating an anti-wafer and an advanced probe card are also disclosed.

Abstract: In one embodiment, a probe for testing integrated circuits includes a body having a tip and a hardening material on the tip. The hardening material helps improve the hardness of the tip. The hardening material thus allows the probe to reliably penetrate a layer to make a good electrical connection with a contact point under the layer, for example. In one embodiment, an electrically conductive coating is deposited over the hardening material.

Abstract: A method for preparing a transmission electron microscopy (TEM) sample is provided which includes removing a portion of a substrate using a focused ion beam tool and securing the removed portion to a support structure to form a grafted structure. The method further includes forming an opening within the support structure to expose an underside of the removed portion and thinning the exposed underside using an ion beam miller tool. In some cases, the step of securing the removed portion to the support structure may include placing the substrate specimen upon a film attached to a mesh grid, positioning the mesh grid upon a framework comprising the support structure such that the substrate specimen is above the support structure, and pushing the substrate specimen through the film onto the support structure. A TEM sample resulting from such methods is also provided.

Abstract: A multi-port memory cell (200) can be formed from seven transistors. Single ended write operations can be performed without a boosted word line voltage or variable power supply. A data value (D/DB) stored in the memory cell (200) can be cleared by shorting complementary data nodes (204-0 and 204-1) together. Write data can then be placed on a bit line. Complementary data nodes (204-0 and 204-1) can then be isolated once again, resulting in the write data being latched within the memory cell (300). An access method (700) for a multi-port memory cell is also described.

Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Abstract: A system and method for transforming databases to maintain compatibility with an associated software application. An initial database associated with an application is formatted using a description language that is transformable by a stylesheet language. After modification of the structure or values of the initial database, a translator using a stylesheet language is applied to the database to transform the database so that it retains compatibility with a revised or updated application. When the application itself is modified, the translator can be used to maintain compatibility between existing databases and the revised application. In one embodiment, the application can be used to program an electronic device.

Abstract: A Phase Locked Loop (PLL) that has a substantially constant gain over a wide frequency range. The frequency range over which the PLL operates is divided into a number of frequency sub-ranges. The circuit includes a mechanism for adjusting the loop gain profile as the PLL moves from one frequency sub-range to another. When the PLL switches to a new frequency sub-range, the loop gain profile is adjusted to a pre-established value. Changes of frequency within each sub-range are then accomplished with the loop gain varying within a pre-established range.

Abstract: A system on a chip (SOC) bus architecture may comprise a plurality of masters operable to request communications over a AMBA-type bus. An arbiter may receive requests and burst control signals directly from the masters. The arbiter may determine a burst length associated with a request and may also grant a master allowance to access the bus. The arbiter may configure a multiplexer to couple the granted master to the bus dependent on the determined burst length.

Abstract: A method is disclosed for obtaining a read-out signal of a pixel having at least a photosensitive element with a charge storage node. Charge carriers are converted from radiation impinging on the photosensitive element. While acquiring charge carriers on said charge storage node, after a time period at least one reset pulse with a predetermined amplitude is applied on said charge storage node, said pulse resetting incompletely the charge carriers acquired at the moment of applying said pulse; and thereafter charge carriers are further acquired on said charge storage node.

Abstract: Methods for fabricating diffusion regions having steep concentration profiles within MOS devices while minimizing junction capacitance degradation are provided. In particular, methods are provided which include patterning a gate structure upon a semiconductor substrate and subsequently etching a recess in exposed portions of the substrate. In some cases, the method includes forming a first dopant region within the exposed portions prior to etching the recess. The method may additionally or alternatively include implanting a second set of dopants into portions of the semiconductor substrate bordering the recess. In either case, the method includes growing an epitaxial layer within the recess and implanting a third set of dopants into the semiconductor topography to form a second dopant region extending to a depth at least within the epitaxial layer.

Abstract: A regulator circuit including output loading sense circuitry where the output loading sense circuitry comprises, in one example, a resistor in the feedback leg of the replica bias regulator, a switch in the feedback leg of the replica bias regulator for bypassing the resistor, and a comparator used to sense the output loading and selectively drive the switch.

Abstract: The present invention describes methods and devices for reading out an image sensor with reduced delay times between the reading out of different lines. The method of a first embodiment reads out each line of an image sensor in at least two overlapping sequences, whereby each sequence comprises a succession of blanking times and pixel readout periods. The timing of the sequences is such that the readout periods of different sequences are interleaved. The method of a second embodiment provides a high-speed column readout by discharging a column bus by a load current modulated in amplitude and time. The method of a third embodiment provides a high-speed column readout by pre-charging a column bus by a load current provided by connecting the column bus to a DC potential. Devices corresponding to each of the methods are also provided.

Abstract: A method and system for universal packaging in conjunction with an automated in-line back-end IC manufacturing process. In one method embodiment, the present invention processes a die-strip through a number of integrated in-line processes that function independently of the die size of the die-strip. A control computer maintains a die-strip map database recording the die size of the die-strip. In-line molding and solder ball attachment processes are then performed and function independently of the die size of the die-strip. Processes that are independent of die size provide a universal packaging manufacturing solution. The present invention then accesses the database to determine the die size for cutting the die-strip based on specifications maintained by the electronic die-strip map database. Sorting, testing and finish assembly processes are then performed.

Abstract: Embodiments of a frequency modulated (FM) demodulator and associated methods are generally described. According to but one example embodiment, an apparatus is disclosed comprising a receiver front-end, to receive a signal from one or more antenna(e) and generate quadrature components of the received signal, and a frequency-shifted, cross-multiplied differentiator demodulator, coupled with the receiver front-end, to generate a demodulated representation of the received signal centered at a select intermediate frequency.

Abstract: A digital signal processor transceiver uses a finite impulse response filter memory to construct a phase integrated angle at each clock cycle. The FIR filter memory is addressed by a multibit pattern and a time count which are used in conjunction to determine the address. Each data word of the FIR filter memory represents the sum of two tap points multiplied by their tap coefficients. Several of the most significant bits of the phase integrated angle are used to address look up tables for the signal's sine and cosine values. The address for the cosine look up table may further be phase compensated. Filter types other than a FIR filter may be used.

Abstract: An apparatus comprising a transceiver circuit. The transceiver circuit comprises a plurality of bus input/outputs (I/Os). The transceiver circuit may be configured to directly couple (i) an analog signal to the bus I/Os when the bus I/Os are in a first state and (ii) a plurality of first digital signals to the bus I/Os when the bus I/Os are in a second state.

Abstract: An emulation and debugging system that includes an in-circuit emulator couplable to a microcontroller. The in-circuit emulator is adapted to execute an event thread in lock-step with the microcontroller. Event information generated as a result of executing the event thread is sampled at selected points and the sampled event information is stored in memory. Trace information is also recorded at the selected points. The sampled event information and the recorded trace information are time-stamped. In one embodiment, a display device is coupled to the in-circuit emulator. The display device is used for displaying analog and/or digital waveforms representing the sampled event information and the recorded trace information. Accordingly, an in-circuit emulator system can also function as an oscilloscope and/or as a logic analyzer, allowing a user to view event and trace information, along with other information, that are generated as part of the debugging process.

Abstract: An apparatus comprising one or more stations. Each of the one or more stations may be configured to receive a signal from a communication channel. The signal generally comprising event detection information. The one or more stations may be configured to share the event detection information.

Abstract: Embodiments of the present invention relate to a method for configuring functional interconnections in a programmable device. The method comprises displaying a graphical user interface, which presents a graphical depiction of the programmable device, selecting a functional user module in the graphical user interface, selecting an interconnect input or output on the user module and displaying a graphical representation of allowable connections for the pin by highlighting those allowable connections in the graphical user interface. The desired interconnection is then selected and selection options for configuring the interconnection can be presented in and selected from a pop-up window or a drop-down list in the graphical user interface.