Abstract: A method of communicating between a host and a USB-connected device is provided, in which a first and second phase of a communications protocol are asynchronously transmitted between the host and the device. A third phase of the communications protocol can also be asynchronously transmitted with the first and second phases. The USB-connected device can be a mass storage device and the communications protocol can be a bulk-only transport protocol having a command phase, a data phase, and a status phase.

Abstract: An apparatus comprising a circuit configured to automatically select a clock mode in response to a state of a clock input.

Abstract: A communication interface for an in-circuit emulation system. The interface uses four pins between a virtual microcontroller (an FPGA emulating a microcontroller) and a real microcontroller under test. The bus is fast enough to allow the two devices to operate in synchronization. I/O reads, interrupt vector information and watchdog information is provided over the bus in a time fast enough to allow execution in lock step. Two data lines are provided, one is bi-directional and one is driven only by the microcontroller. A system clock is provided and the microcontroller supplies its clock signal to the FPGA since the microcontroller can operate at varying clock speeds. The bus is time-dependent so more information can be placed on this reduced-pin count bus. Therefore, instructions and data are distinguished based on the time the information is sent within the sequence. The bus can be used to carry trace information, program the flash memory on the microcontroller, perform test control functions, etc.

Abstract: A method for assigning chip identification (ID) values is disclosed. Unique chip ID values may be assigned to chips (106-0 to 106-5) in a system (100) having multiple branches (112-0 and 112-1). After chip IDs have been assigned to chips of a first branch (112-0) a command processing system (104) may issue an end of branch indication. Chip IDs may then be assigned to chips of a next branch (112-1).

Abstract: The invention enables construction of a microscope that has one or more advantageous characteristics as compared to previous microscopes. The microscope can be small and lightweight and, in particular, sufficiently small and light weight to be portable (e.g., smaller and far lighter than probe station microscopes used for microscopic liquid crystal analysis of a semiconductor device). The microscope can include a small and lightweight bellows that provides zoom capability. The microscope and/or a tripod that is used with the microscope can be implemented to provide objective lens position control capability (with any number of translational and/or rotational degrees of freedom). The microscope can include apparatus for ejecting a hot gas from the microscope to heat a specimen being observed with the microscope.

Abstract: A device capable of operating at both a low power mode and at a high power mode which is connected to a host by a USB connection. The device includes a non-volatile memory which stores the operating state of the device when the host goes into hibernate mode and a flag which indicates that the host has entered the “hibernate” mode. When the device powers up, the previous state of the device is read from the memory. If the previous state was high power and the hibernate flag is set, the device restarts in high power mode without the need of any initialization to determine if the host will allow operation at high power speed mode. The device determines that the host is going into suspend mode (rather than power down mode) by determining if a suspend signal on the USB bus is followed by a power down operation.

Abstract: A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.

Abstract: A method and mechanism for configuring a programmable device are described. The method includes displaying a graphical user interface, which presents a graphical depiction of the programmable device, selecting a functional user module in the graphical user interface, placing the functional user module in the graphical depiction of the programmable device, and automatically generating configuration code to implement the functional user module in the programmable device in accordance with its graphical placement. The functional user module to be implemented can be selected from either a graphically depicted library of functional user modules or a tabular list. Parameter registers and settings options for the user module can be displayed and edited in pop-up windows or drop-down lists.

Abstract: A method of forming a semiconductor structure, comprises exposing a photoresist layer; followed by heating the photoresist layer to a first temperature for 30 seconds to 3 minutes; followed by heating the photoresist layer to a second temperature for 30 seconds to 3 minutes. The second temperature is 5–15° C. greater than the first temperature.

Abstract: A LVDS output driver has been disclosed. One embodiment of the LVDS output driver includes a number of source followers, each of the source followers including a pull-down transistor having a source, a drain, a gate, and a bulk terminal. The embodiment of the LVDS output driver further includes a number of pull-up transistors, each of the pull-up transistors having a source, a drain, and a gate, wherein the drain of each of the pull-up transistors is coupled to the source of a pull-down transistor of the source followers, to output a number of differential signals via the drains of the pull-up transistors. Other embodiments are described and claimed.

Abstract: Disclosed herein is a device and method for adapting an operating speed of a USB peripheral device coupled with a host. In one example, the peripheral device is initially operated at a first operating speed associated with a first power consumption level, and it is determined whether the host will support the peripheral device operating at a second, higher power consumption level. If so, the peripheral device is reconfigured to operate at a second operating speed associated with the second power consumption level. In one example, the peripheral device may be initially operated at an operating speed of approximately 12 Mbps (i.e., full speed USB) so that the peripheral device draws no more than approximately 100 mA of current. In this example, the peripheral device may report a high power descriptor set including a 100 to 500 mA descriptor, and if the host selects the descriptor set, then the peripheral device is can reconfigure itself to operate with an operating speed of approximately 480 Mbps (i.e.

Abstract: A circuit for use in conjunction with a portion of a core of an integrated circuit, for shifting a signal from a first voltage level to a second voltage level, wherein the circuit is formed using the same process type transistors (i.e., low voltage transistors) as are used in the core of the integrated circuit.

Abstract: A method and apparatus for a multi-channel high speed framer is described. In one embodiment, the invention is an apparatus. The apparatus includes a first plurality of pipeline stages suitable for data framing between a link layer and a network interface. The apparatus also includes a first memory coupled to each pipeline stage of the first plurality of pipeline stages, the first memory to store context information at predetermined stage locations for each pipeline stage. The apparatus further includes a first control logic coupled to the first memory and to each pipeline stage of the first plurality of pipeline stages, the first control logic to control transfer of data between the first memory and the first plurality of pipeline stages. Within the apparatus, each stage of the first plurality of pipeline stages is suitable for loading the context information from the first memory through first control logic and performing a sub-function of data framing.

Abstract: A circuit, method and microcontroller apparatus for performing an analog to digital conversion with continuously variable resolution is disclosed. The circuit includes a integrating modulator for converting an analog input signal, corresponding to an input voltage, to a digital signal at its output over an integrate time. The circuit also includes a counter with an enable input coupled to the integrating modulator output. The counter accumulates the number of cycles where the digital signal is positive during the sample period and provides a corresponding conversion result. Further, the circuit has a pulse width modulator; its output gates a clock to the counter enable input. The pulse width modulator is user programmable on-the-fly to set said integrate time and said sample period.

Abstract: A parallel data interface and method is provided herein, which adjusts a timing relationship of a clock signal to not only minimize clock skew, but to also compensate for noise components that may affect one or more paths of a parallel data bus. In some embodiments, the parallel data interface includes a first phase generator coupled to generate a first plurality of time delay pulses, and a first phase selector adapted to select one of the first plurality of time delay pulses to adjust the timing of a clock signal to sample each and every one of the plurality of data signals between minimum setup and hold time thresholds. In some embodiments, the parallel data interface includes a second phase generator coupled to generate a second plurality of time delay pulses, and a second phase selector adapted to select one of the second plurality of time delay pulses to adjust the timing of the clock signal to output the plurality of data signals from the data interface at least an amount of time (i.e.

Abstract: One embodiment of the present invention enables a low performance and low cost microprocessor (or microcontroller) to perform binary demodulation of analog communication signals. Within the present embodiment, three techniques may be utilized to enable this functionality. For example, an analog-to-digital converter sampling rate technique is utilized with an incoming modulated analog communication signal. This sampling rate technique is able to eliminate the need for any reference sine and/or cosine waves during the demodulation process. Next, utilizing sample values produced by the sampling rate technique, a continuous-time sum of products calculation is performed by a central processing unit (CPU) of the microprocessor or microcontroller. The results of the continuous-time calculation then enables the present embodiment to demodulate the binary modulated analog signal.

Abstract: One embodiment of the present invention provides a latch hysteresis receiver circuit having reduced crowbar current. Within the present embodiment, the latch hysteresis receiver circuit comprises an input stage and a latch hysteresis switching element coupled to the input stage. Additionally, the latch hysteresis receiver circuit comprises a pass gate coupled to the latch hysteresis switching element and to an output of the latch hysteresis receiver circuit. It is noted that the pass gate may be for restricting current that flows through the latch hysteresis switching element.

Abstract: A module generally comprising a first transmitter, a detector and a controller. The first transmitter may be configured to transmit through a first physical channel of a connector. The detector may be configured to receive a first status signal but not receive user data through a second physical channel of the connector. The controller may be configured to adjust a power of the first transmitter in response to the first status signal.

Abstract: A method of automated enumeration of one or more devices comprising the steps of (A) generating an enumeration of a plurality of fuses and (B) compiling data for each one of said plurality of fuses, wherein the data comprises (i) one or more schematic path data, (ii) one or more simulation path data and/or (iii) one or more physical location data.

Abstract: A crystal oscillator circuit which does not produce runt pulses when the oscillator is turned on or off. The circuit includes a crystal oscillator, an integrator which integrates the energy in a plurality of pulses, a threshold circuit which is active when the output of the integrator reaches a pre-specified threshold and gating circuits which gate the output of the crystal oscillator to the output terminal only when the threshold circuit has reached the specified threshold.