Patents Assigned to Cypress Semiconductor
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Patent number: 7099818Abstract: Communications between a device and a debugging system are effectuated by programming an ICE with a first logic set, which enables the ICE to establish communications with the device and determine a unique identifier thereof. The ICE communicates the device's unique identifier back to a host computer. The host computer matches the unique identifier to a second logic set and a plug-in module. The host computer then programs the ICE with the second logic set and activates the plug-in module. The second logic set allow the ICE and the device to execute program instructions downloaded with the second logic set in lock-step fashion. The plug-in module allows the host computer to interact in the debugging process as necessary. This achieves flexibility, because any ICE may be programmed to communicate with any device.Type: GrantFiled: March 29, 2002Date of Patent: August 29, 2006Assignee: Cypress Semiconductor CorporationInventors: Craig Nemecek, Steve Roe
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Patent number: 7096340Abstract: One embodiment of the present invention provides a method of memory management. Within the present embodiment, a page register along with supporting logic allows a mode to be selected by a processor at the same time it specifies a particular memory page. The selected mode defines what the subsequent use of the specified memory page will be. For example, this method may decrease overhead when moving between different memory pages by providing a mode that automatically returns to a previous page after a specified page has been accessed.Type: GrantFiled: November 25, 2002Date of Patent: August 22, 2006Assignee: Cypress Semiconductor CorporationInventors: Warren S. Snyder, Eric D. Blom
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Method and circuit for reducing defect current from array element failures in random access memories
Patent number: 7095642Abstract: A defect current contribution elimination technique may be suitable for dynamic random access memories (DRAMs) and other memory devices. A defect current can be eliminated by using an isolation circuit (106) between bitlines (102-0 and 102-1) and an associated sense amplifier circuit (104). Isolation circuit (106) can be controlled by programmable elements, such as fusible links, which are blown at wafer test to isolate the defective bitlines from the sense amplifier circuit. Isolated, defective bitlines may initially float, but based upon the type of defect, such bitlines can be resistively tied to another element, and as a result no DC current will flow. According to another implementation, controllable devices are placed between wordlines (206) and the wordline driver circuits (226-y). A current path through a defective wordline can be similarly cut-off.Type: GrantFiled: March 12, 2004Date of Patent: August 22, 2006Assignee: Cypress Semiconductor CorporationInventors: Richard Parent, David Chapman -
Patent number: 7094707Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas in a hot wall, single wafer furnace is provided. The nitridation process can be carried out rapidly (i.e., at nitridation times of 30 seconds to 2 minutes) while providing acceptable levels of nitridation (i.e., up to 6 at. %) and desirable nitrogen/depth profiles. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.Type: GrantFiled: May 13, 2002Date of Patent: August 22, 2006Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sundar Narayanan
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Patent number: 7092153Abstract: The invention enables construction of a microscope that has one or more advantageous characteristics as compared to previous microscopes. The microscope can be small and lightweight and, in particular, sufficiently small and light weight to be portable (e.g., smaller and far lighter than probe station microscopes used for microscopic liquid crystal analysis of a semiconductor device). The microscope can include a small and lightweight bellows that provides zoom capability. The microscope and/or a tripod that is used with the microscope can be implemented to provide objective lens position control capability (with any number of translational and/or rotational degrees of freedom). The microscope can include apparatus for ejecting a hot gas from the microscope to heat a specimen being observed with the microscope.Type: GrantFiled: September 27, 2002Date of Patent: August 15, 2006Assignee: Cypress Semiconductor CorporationInventor: Nickey Joe Atchison
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Patent number: 7092980Abstract: A programmable analog device that introduces on a single chip a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. Configuration registers define the type of function to be performed, the way in which the analog blocks are to be coupled, the inputs and outputs of the analog blocks, and the characteristics of the analog elements. The configuration registers can be dynamically programmed. Thus, the device can be used to realize a large number of different analog functions and applications.Type: GrantFiled: August 14, 2001Date of Patent: August 15, 2006Assignee: Cypress Semiconductor CorporationInventors: Monte Mar, Warren Snyder
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Patent number: 7093151Abstract: An apparatus comprising a circuit configured to (i) generate an output having a frequency and (ii) adjust the frequency in response to a measured duration of a known time interval associated with an input data stream.Type: GrantFiled: September 22, 2000Date of Patent: August 15, 2006Assignee: Cypress Semiconductor Corp.Inventor: Timothy J. Williams
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Patent number: 7088166Abstract: A low voltage differential signal (LVDS) input circuit with extended common mode range has been disclosed. One embodiment of the LVDS input circuit includes a first resistor coupled between a differential logic circuit and a first input pad, a second resistor coupled between the differential logic circuit and a second input pad, and a first and a second termination resistors coupled to the first and the second input pads, respectively, the first and second termination resistors being coupled to each other in series at a node to produce a common mode reference voltage at the node. Other embodiments are described and claimed.Type: GrantFiled: June 17, 2004Date of Patent: August 8, 2006Assignee: Cypress Semiconductor CorporationInventors: Robert M. Reinschmidt, Dilip Krishnamurthy
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Patent number: 7089175Abstract: A combined in-circuit emulation system and device programmer. A pod assembly used in an in-circuit emulation system has both a real microcontroller used in the In-Circuit Emulation and debugging process as well as a socket that accommodates a microcontroller to be programmed (a program microcontroller). Programming can be carried out over a single interface that is shared between the microcontroller and the program microcontroller and which is also used to provide communication between the real microcontroller and the In-Circuit Emulation system to carry out emulation functions. In order to assure that the emulation microcontroller does not interfere with the programming process for a microcontroller placed in a programming socket, a special sleep mode is implemented in the emulation microcontroller. This sleep mode is activated by a process that takes place at power on in which the a reset line is released with a specified data line held in a logic high state.Type: GrantFiled: November 1, 2001Date of Patent: August 8, 2006Assignee: Cypress Semiconductor CorporationInventors: Craig Nemecek, Steve Roe
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Patent number: 7089133Abstract: A method and circuit provide a system level reset function for an electronic device. An initial reset function is provided under a low voltage condition of supply voltage, such as occur upon first energizing the electronic device. A tunable reset function is also provided, which can first be asserted at a voltage level setting less precise than that setting becomes upon tuning. Further, a boot-up reset function is provided, which provides its reset function at a voltage level setting that is set according to a calibration. Calibration can be based on data stored in a non-volatile memory, and can involve a checksum operation. The electronic device, a microcontroller for instance, is held in a reset state with any of the initial, tunable, and boot-up reset functions.Type: GrantFiled: September 15, 2004Date of Patent: August 8, 2006Assignee: Cypress Semiconductor Corp.Inventors: Timothy Williams, Harold Kutz, Eric Blom, Warren Snyder
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Patent number: 7089338Abstract: A method and apparatus for interrupt signaling. A communication network is described comprising a master device and a slave device that are both coupled to a two wire serial bus for communication. The two wire serial bus comprises a serial data (SDA) line and a serial clock line. The master device controls communication between the master device and the slave device. The slave device is capable of generating an interrupt signal during an idle condition over the SDA line for requesting a communication transaction with the master device. Also, a method is described for recognizing an interrupt at the master device. During an idle condition over the SDA line, the master device reads the SDA line low. Previously, the slave device pulls the SDA line low during the idle condition. The master device recognizes the reading of the SDA line low as an interrupt signal from the slave device requesting the communication transaction.Type: GrantFiled: July 17, 2002Date of Patent: August 8, 2006Assignee: Cypress Semiconductor Corp.Inventors: David Wooten, Stuart Allman
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Patent number: 7086014Abstract: A method to facilitate programming a microcontroller is disclosed. In one embodiment, after a user configures the circuit by selecting circuit parameters and pin-outs, various items are automatically generated to facilitate programming the microcontroller. The generated items may include: application programming interfaces (APIs) for programming the operation of one or more user modules; source code for realizing the user modules in hardware; interrupt vectors to call interrupt service routines for one or more modules; and a data sheet for the circuit.Type: GrantFiled: November 19, 2001Date of Patent: August 1, 2006Assignee: Cypress Semiconductor CorporationInventors: Manfred Bartz, Marat Zhaksilikov, Steve Roe, Kenneth Y. Ogami, Matthew A. Pleis, Douglas H. Anderson
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Patent number: 7085873Abstract: An ATA device access system preferably includes surrogate registers that correspond to ATA registers. A command register can be configured to control data transfer between the ATA and surrogate registers. A status register can be configured to signal completion of data transfer to or from the surrogate registers. Using the ATA device access system, data can be written to the surrogate registers during a write operation with little or no wait and then transferred to the ATA registers without tying up a bus or a processor. Similarly, data can be loaded into the surrogate registers from the ATA registers during a read operation with little or no wait, before being read from the surrogate registers by a processor.Type: GrantFiled: June 21, 2002Date of Patent: August 1, 2006Assignee: Cypress Semiconductor Corp.Inventor: Randall Don Briggs
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Patent number: 7084662Abstract: A variable impedance output driver has been disclosed. One embodiment of the variable impedance output driver includes a first pull-up structure, a pull-down structure, and a comparator, coupled to the first pull-up structure and the pull-down structure, to calibrate the first pull-up structure and the pull-down structure against a reference impedance. Other embodiments are described and claimed.Type: GrantFiled: February 6, 2004Date of Patent: August 1, 2006Assignee: Cypress Semiconductor CorporationInventors: Hari Om, Andrew J. Wright
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Patent number: 7084066Abstract: This invention is directed to a process for etching a semiconductor device using an etchant composition to form a predetermined etched pattern therein. The semiconductor device typically has a plurality of layers. At least one of the layers comprises a refractory metal, refractory metal alloy or refractory metal silicide. The etchant composition contains a high concentration of chlorine. The source (or TCP) power is decreased over that of conventional methods, and the bias (or RF) power is increased. Using such an etchant composition, along with the adjusted power levels, uniform etching and increased oxide selectivity is achieved.Type: GrantFiled: July 3, 2000Date of Patent: August 1, 2006Assignee: Cypress Semiconductor CorporationInventor: T. Frank Wang
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Patent number: 7082540Abstract: A system and method is provided for tracking royalty obligations of a user of intellectual property. The intellectual property can perform program code being sent to a user of a programmable device. The program code is used to configure the programmable device to the functionality of a design owned by an intellectual property vendor. The intellectual property vendor can send an identifier with the code and the programmable device manufacturer can send an embedded code with the shipped, programmable device. The user, when programming the device, will compare the identifier within the code to the embedded code and, if a match results, the user will know that the program contains valuable intellectual property. For each device being programmed with such intellectual property, a computation can occur and the number of thusly programmed devices can be maintained within a resulting royalty payment table.Type: GrantFiled: November 2, 2001Date of Patent: July 25, 2006Assignee: Cypress Semiconductor Corp.Inventors: Nilam Ruparelia, Deepak Sharma
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Patent number: 7078334Abstract: According to one embodiment, a method (100) may include forming a first insulating layer over a semiconductor substrate (step 102), forming a hard mask layer (step 104), and forming a photoresist etch mask having a thickness of less than about 4,000 angstroms (step 106). Such a reduced thickness may conventionally lead to uncontrolled etching and/or may require multiple steps to ensure feature formation. A method (100) may further include etching an opening through at least one half the thickness of the hard mask layer to form a hard mask (step 108) and etching through a first insulating layer without first removing a photoresist layer (step 110). Such etching can essentially consume a photoresist layer, however controllability can be maintained as etching may continue with a hard mask in place.Type: GrantFiled: June 6, 2002Date of Patent: July 18, 2006Assignee: Cypress Semiconductor CorporationInventors: Saurabh Dutta Chowdhury, Mehran Sedigh, Chan Lon Yang, Prabhu Goplana
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Patent number: 7080327Abstract: A method and system for helping a user perform tasks in software. Graphic elements (e.g., icons) are rendered and displayed regardless of which task is being performed. An element can be either active or inactive; user selection of an element with the element active initiates an action in response to the selection while user selection of the element with the element inactive will not initiate the action. The elements are selectively activated and deactivated to guide the user through the tasks according to the order in which the tasks are logically performed. The elements are also selectively activated and deactivated to suggest a hierarchy to the tasks within the logical order of the tasks. Accordingly, the user is guided through the tasks without the need for a help utility such as a wizard.Type: GrantFiled: November 9, 2001Date of Patent: July 18, 2006Assignee: Cypress Semiconductor CorporationInventors: Manfred Bartz, Marat Zhaksilikov
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Patent number: 7080189Abstract: A method of communicating between a host and a USB-connected device is provided, in which a first and second phase of a communications protocol are asynchronously transmitted between the host and the device. A third phase of the communications protocol can also be asynchronously transmitted with the first and second phases. The USB-connected device can be a mass storage device and the communications protocol can be a bulk-only transport protocol having a command phase, a data phase, and a status phase.Type: GrantFiled: May 31, 2002Date of Patent: July 18, 2006Assignee: Cypress Semiconductor Corp.Inventor: Eric J. Luttmann
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Patent number: 7080276Abstract: An apparatus comprising a circuit configured to automatically select a clock mode in response to a state of a clock input.Type: GrantFiled: June 1, 2004Date of Patent: July 18, 2006Assignee: Cypress Semiconductor Corp.Inventor: Timothy J. Williams