Abstract: A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) controlling the background operations in one or more sections of the memory array in response to one or more control signals and (ii) presenting the one or more control signals and one or more decoded address signals to one or more periphery array circuits of the one or more sections.

Abstract: A method and apparatus for automatically detecting the memory size of a serial peripheral interface (SPI) device. Specifically, the present invention describes an SPI interface circuit including a memory controller chip, an EEPROM, a sensing circuit, and a pulldown resistor. In one embodiment, a “READ” command from the controller to the SPI device is sent in a first byte of information transferred between the controller and SPI device. The data Input/Output (D-IO) pin is then driven low for the second byte of information. Next, the D-IO pin is floated and the pin assumes a logic “0” level due to a pulldown resistor. Subsequently, a sensing circuit can detect when and if a non-zero data value passes from the SPI device to the memory controller chip to determine the memory size of the SPI device or the absence of an SPI device.

Abstract: ATA devices, such as mass storage units, have increasingly larger storage sizes that use larger configuration register sizes. A command block format allows the USB/ATA bridge circuit to be used with ATA devices with larger registers and at the same time operates with earlier ATA command block formats.

Abstract: A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.

Abstract: A transmission gate logic circuit (200) can include a supply path (206) connected to an output of a passgate (202). A boost path (208) can be situated between an input of passgate (202) and the supply path (206) and can enable a first supply device (206-0) within the supply path (206) in response to a signal C at the input of passgate (202). A supply path (208) can thus provide a boost at the output node (214) of passgate (202) resulting in faster logic transition times.

Abstract: A method, system, and computer program product for designing an integrated circuit. In one example, a standard library is provided having a plurality of standard circuit cells, and a substitute library is provided having a plurality of substitute circuit cells wherein one or more substitute circuit cells correspond to one or more standard circuit cells and the one or more substitute circuit cells have at least one differing electrical characteristic—such as power consumption, quiescent current consumption, speed/response time, leakage current, etc.—than the corresponding one or more standard circuit cells. An initial circuit design is created using the plurality of standard circuit cells of the standard library; and one or more non-critical timing paths are identified in the initial circuit design, the non-critical timing paths including one or more standard circuit cells.

Abstract: Embodiments of the present invention recite a level shifting circuit for high voltage protection. In embodiments of the present invention, the level shifting circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor coupled in a cascode configuration. The circuit further comprises a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor coupled in a cascode configuration. The level shifting circuit further comprises an output coupled with the source of the first transistor, the gate of the seventh transistor, and with the drain of the second transistor. A first inverter is coupled with a second inverter in series and an input signal conveyed to the first inverter dynamically controls the bias level for said second and sixth transistors.

Abstract: A power management system and circuit comprising instructions stored in computer memory for the prevention of simultaneous coupling of more than one power source to a device under test (DUT). Instructions stored in memory prevent the simultaneous application of power to the DUT from both the in circuit emulator power grid and an external power source. External power applied to the DUT results in at least one activity signal detected by the computer. If no activity signal appears, a fault condition in the DUT is interpreted. If an activity signal is detected, testing continues under control of Debug Software.

Abstract: A method of performing back-end manufacturing of an integrated circuit (IC) device is disclosed. In one method embodiment, the present invention processes a die-strip through a front-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The die-strip is then automatically provided to an end-of-line assembly portion. The die-strip is then processed through an end-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The present embodiment then automatically provides the die-strip to a test assembly portion. The die-strip is then tested by the test portion and then automatically provided to a finish assembly portion. The present embodiment then processes the die-strip through a finish portion which comprises a plurality of sub-stations operating on an in-line basis. Camera systems perform automated visual inspection of dies on the die-strip and maintain a database that can be used for automated reject management.

Abstract: An apparatus for address selection including a first storage element and a second storage element coupled to an input bus. The first storage element stores a first address segment and the second storage element stores a second address segment upon the receipt of respective complementary clock signals. An internal address bus propagates the address segments together.

Abstract: A tester or method of testing a mass storage interface queues error functions for simulation responsive to condition criteria of such storage simulation. Such bridge-chip tester may comprise ATA registers to receive data from an ATA or ATAPI-type interface. A main access emulator may emulate data storage processes responsive to commands of a command register of the ATA registers. A test controller may be operable to load a queue with predetermined error functions to be emulated by the tester. The queue may release error functions of the queue for emulation responsive to data of at least one of the command register and the emulator.

Abstract: A system and method that calculates multiple bytes of data in a single cycle. The invention uses at least two CRC circuits to calculate a CRC value for a string of data. A first CRC circuit is used for calculating multiple bytes at a time. A second CRC circuit is used for calculating a single byte. The first CRC circuit is only used when there are multiple bytes to be processed. If there are other CRC circuits, then data is directed to the appropriate CRC circuit, i.e., the CRC circuit that calculates the appropriate number of bytes, when the number of bytes remaining to be processed is less than the first CRC circuit can process. Otherwise, the data is directed to the second CRC circuit, and must be processed one byte at a time until there is no more data remaining.

Abstract: A class AB analog inverter comprising cascoded n-channel (NMOS) and p-channel (PMOS) transistors. The inverter uses complementary devices, of which one or more may be a first transistor in cascode with a second transistor. The first and second transistors may have the same threshold voltage (VT), or may have different threshold voltages. The class AB inverter provides improved slew rate and low power capabilities for use in mixed-signal integrated circuits such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and active filters.

Abstract: A method for modeling analog signals that may comprise (A) detecting one or more attributed analog signals and (B) modeling the attributed analog signals by adding a signature to each of the one or more attributed analog signals.

Abstract: A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.

Abstract: A method of generating a file suitable for programming a programmable logic device. The method generally comprises the steps of (A) generating a programming item from a plurality of parameters that define a program for the programmable logic device, (B) storing the programming item in a programming field of the file in response to generating, and (C) storing at least one of the parameters in a non-programming field of the file.

Abstract: A method of generating a file suitable for programming a programmable logic device. The method generally comprises the steps of (A) generating a programming item from a plurality of parameters that define a program for the programmable logic device; (B) compressing the programming item to present a compressed item; (C) storing the programming item in a programming field of the file in response to generating; and (D) storing the compressed item in a non-programming field of the file in response to compressing.

Abstract: An automatic transistor threshold measuring circuit (100) can include a current source circuit (102) that can provide increasing amounts of current to a measured transistor (N1) according to current setting values (ICODE). When a gate-to-source voltage of measured transistor (N1) essentially equals a first reference voltage (Vref1), the current setting values (ICODE) is stored. The process is repeated with a second reference voltage (Vref1) to acquire a second current setting value (ICODE) A threshold voltage for the measured transistor (N1) can be calculated according to the reference voltages (Vref1 and Vref2) and stored current setting values (ICODE).

Abstract: An error monitoring system for a transceivers includes a multiplexer and a parity calculating circuit. A comparator has a first input that is coupled to the multiplexer and a second input that is coupled to the parity calculating circuit.

Abstract: A method for multi-bit de-skewing of parallel bus signals is disclosed. The method includes receiving data comprising a multi-bit word and a training pattern. After a first control word of the training pattern is detected, the number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of a parallel bus is calculated. The number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of the parallel bus is transmitted to a bit delay line. The system then outputs a de-skewed data word.