Abstract: An improved furnace system and method is provided to substantially minimize, if not eliminate, ambient air from entering a heated chamber of the furnace system during a critical processing step. The furnace system can be used in, for example, an oxidation step where ambient air containing oxygen is prevented from entering an atmospheric pressure tube by essentially purging potential leak areas with an inert gas, such as nitrogen, at the critical moment during temperature ramp up and ramp down, and prior to temperature stabilization and the introduction of an oxidizing gas. If oxygen is not present within the tube, then a tungsten sidewall surface of a gate conductor, for example, will not inadvertently oxidize at the critical pre- and post-oxidation moments. However, if steam is present where hydrogen is available with oxygen, the underlying polysilicon sidewall surface will selectively oxidize instead of the overlying tungsten.

Abstract: In one embodiment, a transistor is fabricated by forming gate materials, such as a gate oxide layer and a gate polysilicon layer, prior to forming a shallow trench isolation (STI) structure. Forming the gate materials early in the process minimizes exposure of the STI structure to processing steps that may expose its corners. Also, to minimize cross-diffusion of dopants and to help lower gate resistance, a metal stack comprising a barrier layer and a metal layer may be employed as a conductive line between gates. In one embodiment, the metal stack comprises a barrier layer of tungsten-nitride and a metal layer of tungsten.

Abstract: A method for determining the capacitance of an analog/mixed signal circuit, comprising the steps of (A) acquiring a capacitance at a plurality of different input slope rates, (B) verifying each acquired capacitance, (C) determining an average capacitance of said plurality of different input slope rates over a partial average range and (D) determining an accuracy of the capacitance.

Abstract: In one embodiment, a local interconnect layer in an integrated circuit is formed by depositing a first film over an oxide layer and depositing a second film over the first film. The first film may comprise titanium nitride, while the second film may comprise tungsten, for example. The first film and the second film may be deposited in-situ by sputtering. The second film may be etched using the first film as an etch stop, and the first film may be etched using the oxide layer as an etch stop.

Abstract: A method of forming a semiconductor structure is described that includes etching a first metal layer at the bottom of a via in a first insulating layer to expose a second metal layer, wherein the first metal layer is on the second metal layer, and wherein the etching of the first metal layer is not reactive-ion etching. Methods of making semiconductor devices and electronic devices are also described.

Abstract: A circuit, system, and method are provided for regulating the mark-to-space ratio of a clocking signal. In instances where the mark-to-space ratio is targeted at 1:1 (i.e., a 50% duty cycle), then a regulated signal is formed which will produce a 50% duty cycle whenever that regulated signal is forwarded to a buffer which will produce a duty cycle other than 50% if the input signal were not regulated. The regulated signal is derived from a feedback circuit which will take into account the periodic nature of the clocking signal and whatever threshold skews might be attributable to the clock buffer. The feedback signal derives its input from a tap connected to receive the clocking signal from an output of the buffer, and the tap forwards that clocking signal to switching transistors which impute the periodic clocking frequency onto a threshold skewed output which will then form the regulated signal. Any skew resulting from the oscillator will not be passed to the node which bears the regulated signal.

Abstract: A phase frequency detector (PFD) utilizes hysteresis dead zone avoidance while maximizing the linear range and minimizing the power and area consumed by the PFD circuit. The PFD includes a hysteresis in a reset logic gate, which prevents the reset logic gate from switching its output before each of the corrective pulses from the PFD reach final steady state DC voltage values. The PFD response simulates an ideal response, such that linearity is maintained at the phase lock point and throughout a linear range of +/−2&pgr;. In addition, the hysteresis reset logic gate monitors the corrective pulses to insert an appropriate amount of time delay into the PFD reset path without introducing additional delay elements. As a result, the linear range of the PHD is maximized and the power and area consumed by the PFD is minimized, due to the fact that additional delay elements are eliminated from the design.

Abstract: An apparatus comprising a method for receiving, processing and transmitting one or more packets of a plurality of packet types, comprising the steps of (A) receiving the one or more packets, (B) processing the one or more packets, and (C) transmitting the one or more packets. The receiving step may comprise, in one example, (i) receiving a packet, (ii) determining a packet type indicating a type of data contained in the packet based on a packet identifier and (iii) processing the packet based on the packet type. The processing step may comprise, in one example, (i) identifying a length of the frame, (ii) reading a header (and/or footer) of the packet, and (iii) identifying a reusability of a packet type of the one or more packet types in response to the header. The transmitting step may comprise, in one example, (i) retrieving a packet type, (ii) retrieving a packet, and (iii) storing the packet type in the packet.

Abstract: According to one embodiment, a CAM system (100) may include a comparand register (CMPR) index block (106) for monitoring a status of comparand registers within the CAM blocks (104). A CMPR index block (106) may include a free index register set (120). A free head pointer (122) and a free tail pointer (124) can point to a start and end of a list of free comparand index values stored within a free index register set (120). A CMPR index block (106) may also include a busy index register set (126). A busy head pointer (128) and a busy tail pointer (130) can point to a start and end of a list of busy comparand index values stored within a busy index register set (126).

Abstract: A shared wire serial interface between two devices that share a system clock and a single bi-directional serial data line. The clock drives both the system and the interface and is provided over a single clock wire. One device operates as a master, the other as a slave. Since master and slave share the same clock, clock drift error will be zero. Although the start of a data transfer is asynchronous with regard to the system clock, the data transfer itself, is synchronous. In one embodiment, the bit transfer rate is ⅛th the system clock speed in one example and is generated by a state machine, however, any divide may be used. The state machine also signals the output enablers which interleave the data bits on the serial data line. The flow of data on a single data line of the interface is bi-directional in that data from the master is bit interleaved with data from the slave.

Abstract: A high-gain, high-speed differential preamplifier is described, in which a current source is coupled to one input of a differential amplifier and the other input of the differential amplifier is coupled to a sensor. In one implementation, the current source includes a field effect transistor operating in saturation mode and a bipolar junction transmitter in an emitter follower configuration.

Abstract: An improved communication system, receiver, and method are provided that can reduce input voltages received by the receiver whenever those voltages extend upward to the maximum common-mode voltage range. A detect circuit determines whether the input voltages are at or near the maximum range. If so, the detect circuit sends a control signal to a level shift circuit which will reduce the input voltages by a predefined amount. The reduced voltages can then be forwarded to a sense circuit which preferably operates at a power supply voltage that is less than the maximum differential input voltage (i.e., the maximum voltage on the differential pair of signals), or less than the maximum common-mode voltage of the differential input signals. The sense circuit can thereby operate at a relatively wide common-mode voltage range, and utilizes a lower power supply voltage.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a first reference signal and generate a second reference signal. A frequency and a phase of the second reference signal may be (i) adjusted in response to the first reference signal and (ii) held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled and/or substantially zero delay with respect to the first reference signal.

Abstract: An input gate protection circuit has a pass transistor having a source coupled to an input signal. A first voltage range control circuit is coupled to a gate of the pass transistor. A second voltage range is control circuit coupled to the gate of the pass transistor.

Abstract: A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block.

Abstract: In one embodiment, the threshold voltage of a first transistor is adjusted by implanting a dopant through a mask (e.g., photoresist material). The thickness of the mask may be varied to obtain a particular threshold voltage. The mask may be formed such that it covers a first transistor region where the first transistor is to be fabricated, while leaving a second transistor region exposed. This allows an implant step to adjust the threshold voltage of the first transistor and to form a well in the second transistor region.

Abstract: A method is provided for processing a semiconductor topography. In an embodiment, the method includes positioning a semiconductor topography against a carrier plate with a raised section. Such a method preferably allows a larger area capable of producing a target yield of semiconductor devices within dimensional specifications to be obtained than is obtained by positioning the topography against a carrier plate with a flat surface. As such, positioning a topography against a carrier plate with one or more raised sections may form a substantially planar upper surface in a larger area than in an area formed by positioning such a topography against a flat surface carrier plate. Furthermore, such a method is preferably conducted in a single polishing step. As such, a polishing system is provided which includes a carrier plate with a raised section adapted to planarize a semiconductor topography in one polishing step.

Abstract: A circuit, system, and method is provided for regulating the pulse width and/or duty cycle of a signal indirectly or directly used to drive, e.g., a transmitter. The load of the transmitter can be, for example, an optical signal transmitter. The circuit includes a feedback loop that adjusts the output signal so that the lower voltages are chopped at a reference voltage input into the driver. The magnitude of the reference voltage will regulate the pulse width of the output signal, as well as the duty cycle of the output signal. A low input voltage swing is well-suited to be operated upon by the driver circuit to produce a symmetric pulse width that is particularly adapted to high-speed optical data communication applications. The gain and slew rate of the feedback circuit and, predominantly, the comparator and pull-down transistor of the feedback circuit is tuned to ensure the pull-down transistor is always on and, therefore, the comparator will toggle, but within constrained (i.e., regulated) voltage limits.

Abstract: A PC card with a retractable antenna for use in interfacing between a communications device and a wireless network includes an interface card portion and an antenna portion, the interface card portion having a first end, and an opposite second end, the first end having an electrical interface compatible with the communications device, the second end having an opening for slidably receiving the antenna portion, the interface card portion being dimensioned to be inserted into the PC card slot of the communications device, the antenna portion being in electrical communication with the interface card portion and dimensioned to fit inside the interface card portion, the antenna portion being accessible through the opening in the interface card portion by a user, the antenna portion being configured to extend out of the cavity and retract into the cavity of the interface card portion such that when the antenna portion is retracted into the cavity the antenna portion is substantially contained inside the interface c

Abstract: An apparatus comprising a register circuit, a detector circuit and an output circuit. The register circuit may be configured to present a parallel signal in response to (i) a serial input and (ii) a first clock. The detector circuit may be configured to generate a control signal in response to (i) the parallel signal and (ii) a selection signal. The output circuit may be configured to generate an output in response to (i) the control signal and (ii) the parallel signal.