Abstract: The present invention concerns a method for reducing power consumption in a device, comprising the steps of (A) receiving one or more packets, (B) determining a type of each of the one or more packets and (C) suspending, waking, or partially waking the device in response to a particular type of packet.

Abstract: An apparatus for providing arbitration for a dual-port memory. The apparatus may be configured to prevent a write cycle extension during contention between simultaneous read and write operations.

Abstract: An apparatus configured to communicate through a differential bus to a device. The apparatus may be configured to disconnect and reconnect the device in response to an abnormal reset event to provide enhanced electromagnetic compliance (EMC).

Abstract: A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.

Abstract: According to one embodiment, a structure for monitoring a process step may include an etch stop layer (102) formed on a substrate (104) and a trench emulation layer (106) formed over an etch stop layer (102). Monitor trenches (108) may be formed through a trench emulation layer (106) that terminate at an etch stop layer (102). Monitor trenches (108) may have a depth equal to a trench emulation layer (106) thickness. A trench emulation layer (106) thickness may be subject to less variation than a substrate trench depth. A monitor structure (100) may thus be used to monitor features formed by one or more process steps that may vary according to trench depth. Such process steps may include a shallow trench isolation insulator chemical mechanical polishing step. In addition, or alternatively, a monitor structure (100) may be formed on a non-semiconductor-on-insulator (SOI) wafer, but include SOI features, providing a less expensive alternative to monitoring some SOI process steps.

Abstract: An apparatus configured to interface a first clock speed of a multiqueue storage device and a second clock speed of an interface. The apparatus may be configured to control a flow of variable size data packets.

Abstract: A method of forming a semiconductor structure comprises forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.

Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas is disclosed. The nitridation process can be carried out at lower temperatures and pressures than a conventional nitrous oxide anneal while still achieving acceptable levels of nitridation. The nitridation process can be conducted at atmospheric or sub-atmospheric pressures. As a result, the nitridation process can be used to form nitrided gate oxide layers in-situ in a CVD furnace. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.

Abstract: A method for fabricating a bipolar transistor is provided. In some cases, the method may include patterning an epitaxial layer to expose one or more regions of a semiconductor topography. The method may further include depositing an intermediate layer above the exposed regions and remaining portions of the epitaxial layer. A conductive emitter structure may then be formed above and within the intermediate layer. In another embodiment, the method may include etching a first dielectric layer in alignment with a patterned base of a bipolar transistor while simultaneously etching a second dielectric layer in alignment with a patterned emitter structure of the bipolar transistor. In yet other embodiments, the method may include depositing an intermediate layer which is substantially etch resistant to a resist stripping process. In addition or alternatively, the intermediate layer may include etch characteristics that are substantially similar to a conductive layer formed above the intermediate layer.

Abstract: A method is provided for forming a self aligned contact by etching an opening through a low doped or undoped dielectric layer such as phosphosilicate glass. The dielectric layer may be formed on a semiconductor layer which may include regions of monocrystalline silicon and undoped silicon dioxide. A first portion of a dielectric layer may be etched with a first etch chemistry, and a second portion of the dielectric layer may be etched with a second etch chemistry. The first etch chemistry may be substantially different than the second etch chemistry. In this manner, the first etch chemistry may have a substantially different etch selectivity than the second etch chemistry. For example, in an embodiment, the first etch chemistry may be selective to silicon nitride, and the second etch chemistry may be selective to undoped silicon oxide.

Abstract: An apparatus comprising a synchronous circuit configured to (i) shift a JTAG instruction signal in response to a first control signal, (ii) decode the JTAG instruction signal while the JTAG instruction signal is shifted and (iii) latch the decoded JTAG instruction signal in response to a second control signal.

Abstract: A buffer includes a pull-up level shifter coupled to an input signal. A pull-down level shifter separate from the pull-up level shifter is coupled to the input signal. A driver is coupled to the pull-up level shifter and the pull-down level shifter.

Abstract: An interpolation scheme uses cubic subdivision to index a position of an input color value in a color space relative to neighboring vertices. The indexed position of the input color value is expanded and the neighboring vertices are combined together according to the expanded index to generate an output color value.

Abstract: Embodiments disclosed relate to wafer level burn-in of integrated circuits on a semiconductor wafer. One embodiment disclosed performs monitored burn-in on sample wafers from a manufactured lot of wafers and determines a burn-in time for the lot from results of the monitored burn-in. The burn-in on remaining wafers from the lot is then performed for the burn-in time that was determined. Another embodiment disclosed performs burn-in on wafers from a manufactured lot of wafers while monitoring in real-time the burn-in for a subset of wafers in the lot. Using fallout data from the real-time monitoring, a determination is made as to whether the burn-in time is sufficient. If the burn-in time is determined to be sufficient, then the burn-in of the lot is stopped.

Abstract: In one embodiment, a control loop in an electrical circuit includes a variable feed-forward circuit configured to determine a setting of a variable oscillator that would result in a frequency of a first signal approximating a frequency of a second signal. The setting may be used to control the variable oscillator at a time when a phase error between the first signal and the second signal is negligibly small (e.g., substantially zero), thus allowing for relatively short loop convergence time.

Abstract: A crystal-less oscillator circuit with trimmable current control. In one embodiment, the present invention provides an oscillator circuit comprising a digital to analog converter circuit for generating a current, a band gap reference circuit for generating a voltage, and a relaxation oscillator circuit for creating a frequency based on the current and the voltage. In one embodiment, the digital to analog converter circuit comprises a trimmable current control. In one embodiment, the relaxation oscillator circuit is coupled to a frequency doubler circuit wherein the frequency is passed through the frequency doubler circuit for generating a second frequency. In another embodiment, the present invention provides a phase locked loop circuit comprising a phase detector circuit and the aforementioned oscillator circuit. In another embodiment, the present invention provides a microcontroller comprising a phase locked loop circuit comprising a phase detector circuit and the aforementioned oscillator circuit.

Abstract: A dual damascene interconnect structure, produced using etch chemistry based on C2H2F4, includes (i) an etch stop layer of either undoped silicon oxide or doped silicon oxide, and (ii) dielectric layers both above and below the etch stop layer of the other (i.e., when the etch stop layer comprises undoped silicon oxide, the dielectric layers above and below the etch stop layer independently comprise a doped silicon oxide; and when the etch stop layer comprises doped silicon oxide, the dielectric layers above and below the etch stop layer independently comprise an undoped silicon oxide).

Abstract: A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.

Abstract: An apparatus comprising a polarity switch. The polarity switch may comprise a number of transmission gates. An output of the polarity switch may selectably present either (i) a signal that varies in response to a control signal or (ii) a predetermined logic level that is independent of the control signal.

Abstract: A microprocessor system is provided that includes a first memory bank having a first base address and a second memory bank having a second base address. A memory controller is adapted to register the first and second base addresses. A swap command is adapted to instruct the memory controller to swap the first and second base addresses. A microprocessor issues the swap command. The memory controller includes a first base address register adapted to register the first base address and a second base address register adapted to register the second base address. A command register is adapted to register the swap command. In one embodiment, the first memory bank is a DRAM bank and the second memory bank is a ROM bank. The swap command instructs the memory controller to swap the first and second base addresses before temporary storage is established in the DRAM bank.