Abstract: A content addressable memory (CAM) device (100) may include a number of blocks (102-[n?1, n, n+1]) that each generate CAM search results and result compare circuits (104-[n?1, n, n+1] that receive CAM search results from multiple blocks (102-[n?1, n, n?1]), and compare at least a portion of such CAM search results. According to such a comparison result, a compare circuit (104-[n?1, n, n+1]) can generate an output CAM search result for subsequent comparison with CAM search result in another compare circuit (104-[n?1, n, n+1]).

Abstract: According to one embodiment, a shallow trench isolation (STI) method (500) may include forming an etch mask layer over both a first and second substrate side (504). An etch mask layer over a first substrate side (506) may be patterned to form a STI etch mask, and trenches may be etched into a substrate (508). A trench dielectric layer can be formed over a first substrate side (510). An etch mask layer formed over a second substrate side can be etched (512), reducing and/or eliminating stress that may deform a substrate or otherwise adversely affect STI features. A trench dielectric may then be chemically-mechanically polished (step 514).

Abstract: An apparatus comprising one or more logic circuits. The logic circuits may be configured to provide computation. The one or more logic circuits generally comprise dedicated logic within a programmable logic device (PLD).

Abstract: According to one embodiment, verifying a reticle may include patterning an inspected layer (102-2) according to a reticle pattern, depositing a contrast enhancing layer (104-0) on a patterned layer (102-2), and inspecting a reticle patterned formed in the inspected layer (102-2).

Abstract: A method of making a semiconductor structure includes determining a polish time which is sufficient to planarize a layer on a semiconductor substrate. The layer is polished for the polish time to planarize the layer, and then the layer is polished to a predetermined thickness. The semiconductor structures can be used to make a semiconductor device.

Abstract: A method for cleaning a plasma reactor clamber part (100) may include dipping the chamber part in a solvent (102) that may dissolve a material that has been redistributed on the chamber part by a reactive plasma. A chamber part may then be rinsed (104), ultrasonically cleaned (106) in a ultrasonic cleaning liquid, and then rinsed again with a liquid that may evaporate at a lower temperature than an ultrasonic cleaning liquid (108). A chamber part may then be blown dry (110) and baked (112). In addition, or alternatively, a method may also include plasma cleaning a chamber part (202).

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract: Embodiments of the present invention provide a drive and biasing circuit for an input/output stage of a device. Embodiments of the present invention provide live-insertion protection by driving and biasing various nodes in the input/output stage. Embodiments of the present invention also provide over-voltage protection by biasing various nodes in the input/output stage during normal and live-insertion operating conditions. Embodiments of the present invention utilize the voltage on the supply and/or voltage present on the input/output terminal to provide the drive and bias voltage levels. Embodiments of the present invention are thus able to turn off current paths and protect various junctions against breakdown during over-voltage and live-insertion operating conditions.

Abstract: A process for fabricating a semiconductor structure comprises depositing a nitride layer on a semiconductor substrate with a first tool, and depositing an anti-reflective layer on the semiconductor substrate with the first tool. The nitride layer includes silicon and nitrogen.

Abstract: A method and system for calibrating a time constant within an integrated circuit. A voltage storage element is charged, and the time required to achieve a reference voltage on the storage element is measured. The measured time is compared to a desired time. It necessary, an adjustable impedance is modified to change the charging time, and the cycle may be repeated until the charging time matches the desired time. In this novel manner, an actual RC time constant, as rendered in a particular integrated circuit, is measured and potentially adjusted to match a desired time constant. Advantageously, configuration information of the adjustable impedance may be communicated to other circuitry within the integrated circuit to enable such circuitry to implement the same RC time constant in analog signal processing. Consequently, embodiments of the present invention overcome incidences of wide tolerance in passive components implemented in integrated circuits. Beneficially, no external test equipment is required.

Abstract: An apparatus comprising a peripheral device and a host device. The peripheral device may be connected to the host device. The speed of the peripheral device may be adjusted in response to one or more predetermined conditions.

Abstract: A scheme (e.g., one or more methods, circuits and/or architectures) for detecting the difference in frequencies between two periodic (e.g., clock) signals and/or for reliably assuring the frequency of an oscillating circuit (e.g., a voltage controlled oscillator [VCO], a phase locked loop [PLL] containing a VCO, etc.). The present invention is particularly useful for clock recovery in data communications devices and more particularly in asynchronous transfer mode (ATM) devices, such as SONET/SDH transmitters, receivers and/or transceivers.

Abstract: According to one embodiment, a programmable logic assembly (200) may include a nonvolatile memory (202) may be coupled to an associated volatile programmable logic device (PLD) (204). Built-in-self-test (BIST) data (208) may be stored in a nonvolatile memory (202) that places the volatile PLD (204) in a self-test configuration. If a volatile PLD (204) passes a self-test, user data (210) may be stored in a nonvolatile memory (202) that places a volatile PLD (204) into a user determined configuration.

Abstract: A method of forming a semiconductor structure is described that includes etching a trench in a semiconductor substrate, wherein an oxide layer overlies the semiconductor substrate, and a nitride layer overlies the oxide layer; and cleaning the semiconductor substrate while simultaneously performing a pull back of the nitride layer. Methods of making semiconductor devices and electronic devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods are also described.

Abstract: Embodiments of the present invention provide for generating a sampled differential pattern signal with reduced jitter. In one embodiment of the present invention, a seed frequency generator provides a differential seed frequency signal. The differential seed frequency signal is converted to a single ended seed frequency signal by a differential-to-single ended converter. The pattern generation logic utilizes the single ended seed frequency signal to generate single ended pattern signals. Single ended-to-differential samplers then generate a sampled differential pattern signal by sampling the single ended pattern signal according to the differential seed frequency signal.

Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Abstract: A mask simulation process is introduced into a conventional OPC procedure, prior to simulation of a photoresist pattern. Reticle simulation may be achieved using very short wavelengths of light as compared to the mask feature size. Alternatively, reticle simulation may be made through adjustments in a computer aided design process.

Abstract: A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.

Abstract: A dummy structure pattern for fabricating a substantially planar surface within an inactive region of a semiconductor topography is provided. In particular, a semiconductor topography is provided which includes an inactive region comprising a sacrificial annular dummy structure configured to surround an area larger than a square of a minimum critical dimension of a device arranged within an active region of the semiconductor topography. In a preferred embodiment, the area is exclusively designated for a formation of an isolation structure within the semiconductor substrate of the semiconductor topography. As such, a semiconductor topography is provided which includes a separate isolation structure arranged within a spacing of a contiguous isolation structure, which is arranged in a grid pattern within a portion of a semiconductor substrate. Moreover, a semiconductor device is provided which includes an inactive region with a plurality of similarly sized and uniformly arranged annular diffusion regions.

Abstract: In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.