Abstract: An apparatus comprising a first compare circuit, a second compare circuit and a memory. The first compare circuit may be configured to present a first match signal in response to a first address and a second address. The second compare circuit may be configured to present a second match signal in response to the first match signal, a first write enable signal and a second write enable signal. The memory may also be configured to present the first and second write enable signals. In one example, the memory may be configured to store and retrieve data with zero waiting cycles in response to the second match signal.

Abstract: A method of fabricating a semiconductor package that may contain two or more dies. The method generally comprises the steps of (A) mounting a first die having a first side on an assembly apparatus and (B) mounting a second die having a second side and an adjoining third side on said assembly apparatus. The second die may be oriented such that (i) the second side and the third side both face the first side and (ii) the second side and the third side are both substantially nonparallel to the first side.

Abstract: An apparatus comprising a latch circuit, a non-volatile storage circuit, and a switching circuit. The latch circuit may be configured to be dynamically programmable. The non-volatile storage circuit may be configured to be re-programmable. The switching circuit may be configured to transfer data from (i) the non-volatile memory element into the latch circuit in response to a first control signal and (ii) the latch circuit into the non-volatile memory circuit in response to a second control signal.

Abstract: An asynchronous memory device includes parallel test circuitry configured to interface with a single-ended output data path of the memory device and, in some cases, to provide a measure of a slowest cell access time for the memory device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom. For example, the first circuitry and the second circuitry may be configured as a wired NAND and wired NOR combination. In some cases, one or more of the cells may be included within a redundant row or column of the memory device.

Abstract: A circuit configured to match an impedance of a first pin and a second pin coupled to a transmission line. A first resistor is generally coupled to the first pin and a second resistor is generally coupled to the second pin. The first and second resistors may be coupled to a common node to provide an output voltage level independent of process corner and temperature variation.

Abstract: An apparatus comprising a first circuit and a timing circuit. The first circuit may be configured to generate an output clock signal that may compensate for oscillation build-up and stabilization time after a power up. The timer circuit may be configured to provide timing in response to the output clock signal.

Abstract: An apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first control signal, (ii) a second control signal and (iii) the adjustment signal in response to a rate of an input signal.

Abstract: A circuit comprising (i) one or more input paths, (ii) one or more output paths, and (iii) one or more switch circuits. The switch circuits may be configured to connect one or more of said input paths to one or more of said output data in response to one or more control signals. The present invention may be used to read and/or write data in one or more modes of operation such as 9-Bit Big Endian Write, 9-bit Little Endian Write, 18-bit Big Endian Write, 18-bit Little Endian Write, a 36-bit Write, 9-Bit Big Endian Read, 9-bit Little Endian Read, 18-bit Big Endian Read, 18-bit Little Endian Read, 36-bit Read or other mode.

Abstract: An apparatus comprising a flag generation circuit configured to generate an empty flag signal in response to (i) a read clock, (ii) a write clock and (iii) a look ahead bitwise comparison configured to detect when a write count signal minus a read count signal is equal to 1.

Abstract: A circuit comprising a memory array and a control circuit. The memory array generally comprises a plurality of storage queues. Each of the storage queues may be configured to (i) receive and store an input data stream and (ii) present an output data stream. The storage queues may be configured to operate either (i) independently or (ii) in combination to store the input data streams, in response to one or more control signals. The control circuit may be configured to present the one or more control signals to control an operation of the plurality of storage queues. The control signals may be configured to control the configuration of the plurality of storage queues.

Abstract: An electrically erasable programmable logic device (EEPLD) cell (100) is disclosed. A folded floating gate (110) and folded select gate (108) can form two parallel read current paths (Isense0 and Isense1). A first read current path (Isense0) may be formed between a first semiconductor region (104) and a second semiconductor region (106-0), and may be controlled by a first floating gate portion (110-0) and a first select gate portion (108-0). A second read current path (Isense1) may be formed between the first semiconductor region (104) and a third semiconductor region (106-1) that is coupled to a second semiconductor region (106-0). A second read current path (Isense1) may be controlled by a second floating gate portion (110-1) and a second select gate portion (108-1).

Abstract: A method and apparatus for local and global power management in a programmable analog circuit. Specifically, the present invention describes an array of programmable analog blocks. Each block contains current mirror circuits that are coupled in parallel fashion. The mirror circuits function to increase current consumption in a corresponding operational amplifier more current when enabled. Global power management is achieved by increasing and decreasing the bias voltage that is applied to the array. Global configuration bits select the bias voltage value, including electrically disabling the bias voltage from the array of programmable analog blocks. Local power management is provided by enabling or disabling mirror circuits with local configuration bits to adjust the performance in an operational amplifier contained within a corresponding programmable analog block. A microcontroller controls the local and global management of power through the programmable analog block.

Abstract: A PC card with a retractable antenna for use in interfacing between a communications device and a wireless network includes an interface card portion and an antenna portion, the interface card portion having a first end, and an opposite second end, the first end having an electrical interface compatible with the communications device, the second end having an opening for slidably receiving the antenna portion, the interface card portion being dimensioned to be inserted into the PC card slot of the communications device, the antenna portion being in electrical communication with the interface card portion and dimensioned to fit inside the interface card portion, the antenna portion being accessible through the opening in the interface card portion by a user, the antenna portion being configured to extend out of the cavity and retract into the cavity of the interface card portion such that when the antenna portion is retracted into the cavity the antenna portion is substantially contained inside the interface c

Abstract: An apparatus including a driver and an adjustment circuit. The driver circuit may be configured to generate an output signal in response to a clock input signal and an adjustment signal. The adjustment circuit may be configured to generate the adjustment signal in response to the output signal. The adjustment signal may be configured to correct a duty cycle of the output signal.

Abstract: An apparatus that may be configured to generate a wireless radio signal in response to one or more first data signals. The wireless radio signal may comprise a single frequency hopping sequence configured to support one or more peripheral wireless network devices. The apparatus may also be configured to generate the one or more first data signals in response to the wireless radio signal.

Abstract: Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1.

Abstract: An apparatus comprising an analog delay line and a control circuit. The analog delay line may be configured to generate an output signal in response to an input signal, a first control signal, and a second control signal. A phase of the output signal may be (i) coarsely adjustable with respect to the input signal in response to the first control signal and (ii) finely and continuously adjustable in response to the second control signal. The control circuit may be configured to generate the first and the second control signals in response to the input signal and the output signal.

Abstract: According to one embodiment, a content addressable memory (CAM) can include at least one match line (404), series-coupled transistor pairs comprising match transistors (402-0 to 402-n) and switch devices (422-0 to 422-n), bit match indicator signals (406-0 to 406-n), mask cell value signals (412-0 to 412-n), a match line precharge limiting device (414), a match line precharge control device (416) and an amplifier circuit (432). This configuration can allow for the regulation of the match line (404) discharge path through a discharge control device (410) and a match indication feedback device (426). This, in turn, can allow for match line (404) precharging while at least one of the bit match indicator signals (406-0 to 406-n) is in an intermediate, or approximately half-VDD, level that is consistent with relatively low power precharging of the applied comparands.

Abstract: A method and apparatus for functionality change in an integrated circuit chip includes bonding pads by which the functionality of the chip may be selected. Bonding pads are connected to a decoder which determines which path of a predetermined number of paths is to be chosen to provide the selected function. Control signals are fed to logic circuits in predetermined portions of the remainder of the integrated circuit chip to control functions of sub-circuits within the various portions of the integrated circuit chip.

Abstract: An apparatus comprising a first one or more threshold devices, a second one or more threshold devices and a logic device. The first one or more threshold devices may be configured to control an output. The second one or more threshold devices may be configured to receive the output. The logic device may be (i) coupled to the second one or more threshold devices and (ii) configured to provide a feedback to the first one or more threshold devices. The feedback may be configured to force a reset condition if a metastable event occurs.