Abstract: An oscillator circuit configured to generate an output signal having a frequency comprising a current source, a trim circuit, and one or more capacitors. The current source may be configured to generate a temperature independent current in response to a first adjustment signal. The trim circuit may be configured to generate the first adjustment signal. The one or more capacitors may be configured to charge to a controlled voltage using the temperature independent current. The controlled voltage may regulate a variation of the frequency of the output signal.

Abstract: An apparatus comprising a first circuit configured to present one or more control indication signals and (ii) a control clock signal in response to (i) one or more select signals, (ii) one or more clock signals and (iii) one or more divider control signals. The first circuit may be configured to select an active channel from a plurality of channels in response to the one or more select signals.

Abstract: An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.

Abstract: The present invention provides a circuit for writing a particular sized data word from a common input to a number of individual memory cells in a memory array and reading a particular sized data word from the individual memory cells to a common output. The size of the word written to the memory cells can be larger, smaller or the same as the size of the word read from the memory array. The present invention uses a multi-bit write counter to distribute a write timing signal to a number of multiplexer blocks and a multi-bit read counter to distribute a read timing signal to a number of sense amplifier blocks. Each of the multiplexer blocks receives both a data input signal from the common input and the write timing signal continuously when the circuit is in operation. Each of the sense amplifier blocks receives data from the memory array and a read timing signal at all times.

Abstract: A method is provided for processing a semiconductor topography. In particular a method is provided in which a greater pressure may be applied to a first portion of a semiconductor topography than in a second portion of the topography. As such, a method is provided in which a portion of an upper layer in a region adjacent to an outer edge of the semiconductor topography is polished at a faster rate than a portion of the upper layer in a region comprising the center of the topography. Consequently, the method may subsequently provide a manner in which a substantially planar upper surface may be formed across a semiconductor topography including a region adjacent to an outer edge of the semiconductor topography. Alternatively, regions of an upper layer of a semiconductor topography polished at a faster rate than other regions may occur at various locations across the topography.

Abstract: An apparatus comprising an array of storage elements, a first circuit, and a second circuit. The array of storage elements may be configured to (i) store a first bit of data in response to a write address and a first edge of a first clock signal, (ii) store a second bit of data in response to the write address and a second edge of the first clock signal, and (iii) present one or more of the first and second bits in response to a read address. The first and second edges of the first clock generally have opposite polarities. The first circuit may be configured to generate the first clock signal in response to a serial data stream and a strobe signal. The second circuit may be configured to generate the write address and the read address in response to the first clock signal and a second clock signal.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.

Abstract: The present invention provides an integrated parallel and serial programming interface that can be selected between either a parallel programming mode or a serial programming mode. The present invention provides a control logic circuit for selecting between the parallel and serial modes. The present invention also includes a parallel and serial detection circuit. The control logic sends a signal to an interface circuit that selects between a serial programming mode and a parallel programming mode based on the outputs of the parallel and serial detection circuits.

Abstract: A test circuit generally comprising a tester connected to a socket for holding a device under test. The device may be configured to have (i) a first function and (ii) a final function. The tester may be configured to (i) stimulate the first function with a test signal to present a first output signal, (ii) stimulate the final function with the first output signal to present a final output signal; (iii) measure a result between the test signal and the final output signal, and (iv) allocate the result between the first function and the final function to disperse a measurement error in the result.

Abstract: One embodiment of the present invention is an improved feedback amplifier circuit having a variable closed loop gain which avoids including switching elements in its feedback network and maintains a constant output voltage window for an input signal having a wide dynamic range. That is, the switching elements are not on the active feedback path (e.g., they are isolated from the active feedback path). In this manner, the gain of the amplifier circuit may be determined only by the feedback resistance which can be more easily controlled through the use of precision resistors. Additionally, by removing the switches from the feedback network, the parasitics associated with each switch may also be removed from the feedback path of the amplifier circuit. Accordingly, the bandwidth of the feedback amplifier circuit can be controlled more effectively. Specifically, the present embodiment avoids locating the switching functionality in the feedback network by changing the output stage of the feedback amplifier circuit.

Abstract: A method of converting or translating a layout or schematic netlist to a simulation netlist, comprising the steps of identifying net-shorting elements in the layout or schematic netlist and automatically replacing at least one such net-shorting element with an RC network to generate the simulation netlist.

Abstract: A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block.

Abstract: A programmable logic device comprising a plurality of configuration blocks that may be configured to store configuration information for configuring the programmable logic device. The configuration blocks may be simultaneously programmed.

Abstract: The present invention is directed to a buffer improvement for higher speed operation. A buffer may include at least two buffer stages, which may include a first buffer stage and a second buffer stage. A voltage conversion circuit is disposed between the first buffer stage and the second buffer stage. The voltage conversion circuit is suitable for acting as a delay between the first buffer stage and the second buffer stage. Additionally, the first buffer stage may be driven directly, thereby increasing buffer speed.

Abstract: A Universal Serial Bus to parallel bus bridge includes a Universal Serial Bus port that receives a serial bit stream of data and commands in a Universal Serial Bus protocol from a USB host computer. A parallel bus port on the bridge includes parallel port registers and state machines coupled to a peripheral device. A USB controller core is coupled between the Universal Serial Bus port and the parallel bus port and converts data and commands between the Universal Serial Bus protocol and the parallel bus protocol. A sequencer is coupled between the USB controller core and the parallel bus port. A sequence of sequencer commands is loaded into memory in the USB bridge and used by the sequencer to perform a sequence of parallel port operations. The sequencer performs the commands autonomously without intervention from the USB host computer.

Abstract: A communication node is configured to automatically select an optimum common operational mode between itself and a link partner. The communication node sends advertisement packets across a fiber optic medium in order to broadcast its operational capabilities to the link partner. These operational capabilities may include 10BASE-FL and 100BASE-FL. Transitions may be inserted between the advertisement packets which may include clock pulses, data pulses and transitions. The communication node may be attached to a network having a bus architecture and may further be configured to identify an idle signal.

Abstract: A circuit configured to generate an output signal having a first frequency in response to a clock signal having a second frequency. The output signal may be in a first state and a second state for an equal number of half-cycles of the clock signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.

Abstract: An apparatus comprising a number of cross-coupled charge pump stages configured to generate an output voltage in response to (i) a supply voltage, (ii) a first signal, and (iii) a second signal, where the output voltage has a greater magnitude than the supply voltage.

Abstract: A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature (PTAT) and be configured to vary a refresh rate of a memory cell in response to changes in temperature.