Abstract: An apparatus comprising a circuit configured to generate an output voltage having a magnitude greater than a supply voltage, where the output voltage is (i) a positive high voltage when a first input is in a first state and a second input is in a second state and (ii) a negative high voltage when the first input is in the second state and the second input is in the first state.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a first voltage level and a first control signal in response to (i) an input signal having a second voltage level, (ii) an enable signal, and (iii) a plurality of node voltages. The second circuit may be configured to generate the plurality of node voltages in response to the first control signal. The first circuit may be configured to limit the first voltage level.

Abstract: The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input buffers of both the address path and the clock path include input buffer cells configured to reduce timing delay differences caused by process variations while minimizing current leakage. An exemplary input buffer cell described herein includes a first inverter stage with a pair of NMOS devices connected in series with a PMOS device and a second inverter stage having an additional PMOS device connected along a feedback path around an inverter. The PMOS device along the feedback path operates to assist the pair of NMOS devices to pull a voltage input to the inverter to a high logic state, when an input to the cell is held low, to prevent leakage current through the inverter.

Abstract: A method for dynamically selecting an input threshold on an input pin comprising the steps of (A) generating one or more control signals from a user selectable register and (B) selecting the input threshold from a plurality of thresholds in response to at least one of the control signals.

Abstract: The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus in which a concentration of oxygen at flash striking is greater than a concentration during etching.

Abstract: A method for tuning the frequency of oscillation of a clock signal, comprising the steps of (A) analyzing the rate of an incoming data stream to generate one or more control signals and (B) adjusting said frequency of oscillation in response to said one or more control signals.

Abstract: An apparatus comprising a circuit that may be configured to generate an output in response to a first and a second input. The circuit may be automatically biased in response to the first and second inputs.

Abstract: A circuit comprising a filter circuit and a delay circuit is disclosed. The filter circuit may be configured to present an output signal in response to (i) an input signal having one or more glitches and (ii) a control signal having a plurality of transitions between a first and a second state. The delay circuit may be configured to generate the control signal such that the output signal is generated without glitches. In one example the delay circuit may dynamically adjust the control signal in response to a period of the input signal.

Abstract: A method for plasma etching, comprising etching a structure with a plasma prepared from a gas mixture comprising: (i) an etching gas, and (ii) a strained cyclic (hydro)fluorocarbon gas, has a high etch selectivity of oxide versus nitride, and is particularly useful in a SAC etch process.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a frequency that varies in response to (i) a voltage signal and (ii) a load. The second circuit may be configured to generate the load by coupling one or more resistive devices to a reference node in response to a control signal.

Abstract: Timing characterization/analysis of a number of circuit blocks of a library or an integrated circuit, where each circuit block has an associated rise threshold value and fall threshold value, is performed using a common rise voltage threshold value equal to a minimum one of the rise threshold values of all the circuit blocks and a common fall threshold value equal to a maximum one of the fall threshold values of all the circuit blocks. The rise threshold value of each of the circuit blocks may be determined through an iterative process in which a new rise threshold is determined for an input corresponding to an output threshold value equal to the previous rise or fall threshold. Similarly, the fall threshold value of each of the circuit blocks may be determined through an iterative process in which a new fall threshold is determined for an input corresponding to an output threshold value equal to the previous rise or fall threshold.

Abstract: An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii), a don't care state.

Abstract: A method of forming a field oxide or isolation region in a semiconductor die. A nitride layer (over an oxide layer disposed over a substrate) is patterned and subsequently etched so that the nitride layer has a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the nearly vertical sidewall of the nitride layer. A field oxide is then grown in the recess using a high pressure, dry oxidizing atmosphere. The sloped sidewall of the substrate effectively moves the face of the exposed substrate away from the edge of the nitride layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and a nearly non-existent bird's beak.

Abstract: The invention concerns a method for simultaneously forming a metallization and contact structure in an integrated circuit. The method involves the steps of etching a trench dielectric layer of a composite structure having a semiconductor substrate with an active region, a gate structure thereon, at least one dielectric spacer adjacent to the gate structure, a contact dielectric layer over the semiconductor substrate, the gate structure and the dielectric spacer, an etch stop layer over the contact dielectric layer, and a trench dielectric layer over the etch stop layer, to form a trench in the trench dielectric under etch conditions which do not substantially etch the etch stop layer; thereafter, forming an opening in the etch stop layer and the contact dielectric layer by etching under conditions which do not damage the gate structure to expose the active region; and depositing a conductive material into the opening and the trench.

Abstract: A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. A delay of the output clock signal may be identical when operating in either the first mode or the second mode.

Abstract: An apparatus comprising a first memory, a second memory, a control circuit and a flag circuit. The first and second memories may each be configured to store data received from a first data input and present data to a first data output. The control circuit may be configured to control data stored in response to a write clock and control data presented in response to a read clock. The flag circuit may be configured to generate one or more composite flags in response to the first memory and the second memory.

Abstract: A method for stress testing a memory array comprising the steps of (A) setting all memory cells in the memory array to a first digital state, (B) selecting all blocks of the memory array and (C) setting all wordlines in the memory array to a second digital state.

Abstract: The invention relates to an automatic documentation tool and associated method. The method includes embedding comments into a plurality of source files defining the design, creating a configuration file including parameters associated with each source file, and extracting the comments from each source file responsive to the parameters. The method is capable of operating on a plurality of source files originating from a plurality of design tools. The method is capable of sorting through keywords preceding each comment and ordering the comments according to a user's request. The method is capable of receiving register definitions from a header file.

Abstract: An apparatus configured to store and present data. The apparatus may comprise a plurality of storage elements configured to store one or more wordline signals. Each of the plurality of storage elements may be implemented within a memory cell.

Abstract: A dual port memory comprising a memory array, a first address circuit, a second address circuit, a timing circuit, a first data circuit and a second data circuit. The memory array may be configured to (i) write information to a first port or (ii) read information from a second port in response to (i) one or more first timing signals and (ii) one or more second timing signals. The first address circuit may be configured to present one or more first control signals in response to one or more first address signals. The second address circuit may be configured to present one or more second control signals in response to one or more second address signals. The timing circuit may be configured to present the one or more first timing signals and the one or more second timing signals in response to the one or more first control signals and the one or more second control signals. The first data circuit may be configured to read or write information from the first port of the memory array.