Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a differential intermediate signal in response to a differential input signal. The second circuit may be configured to generate one or more output signals in response to said differential intermediate signal.

Abstract: A programmable logic device comprising a first plurality of logic blocks each comprising a first number of I/O macrocells, a second plurality of logic blocks each comprising a second number of I/O macrocells and a configuration circuit configured to enable one or more of said first plurality of logic blocks and/or one or more of said second plurality of logic blocks.

Abstract: A circuit comprising a memory array having a first region, a second region, a plurality of bitlines and an X-decoder. A plurality of transistors may each coupled between the first and second regions, where each of the transistors may be configured to (i) separate the first and the second region during a read operation and (ii) join the first and the second region during a write operation. Alternatively, a plurality of memory regions may be implemented, each separated by another plurality of transistors.

Abstract: A circuit comprising a first counter, a second counter, a third counter and a decoder, where the decoder may be configured to present a locked output signal. The first counter may present a first output signal in response to a start of frame signal and one or more control signals. The second counter may be configured to present a second output signal in response to the start of frame signal and the first output signal. The third counter may present a tracking control signal to the first counter in response to one or more of the control signals.

Abstract: A lead frame assembly includes one or more lead frames each defining a plurality of package locations organized in rows and columns. An injection molding system includes a plurality of culls, each cull being connected to the frame(s) through a plurality of subrunners. Each subrunner delivers molding compound from one of the culls to a respective column of package locations. A plurality of through gates are disposed between adjacent package locations within each column, each through gate supplying molding compound from one package location to a next adjacent package location within the column, each package location being filled with molding compound in turn from the preceding package location. The need for subrunners between adjacent columns of package locations is eliminated, allowing a higher density of package locations within the lead frame(s), reducing materials and labor costs, and increasing manufacturing productivity.

Abstract: A power-on-reset circuit that may be configured to present a power-on-reset signal in response to a voltage. The power-on-reset circuit may comprise a voltage detector, a first analog delay circuit and a feedback loop. The first analog delay circuit may be coupled to an output of the voltage detector. The feedback loop may be coupled an output of the power-on-reset circuit to an input of the power-on-reset circuit.

Abstract: A method of testing an integrated circuit having a layout structure which includes a plurality of branch structures, the method comprising the steps of: (A) generating a control current in response to an input reference; (B) establishing a respective branch current through each of the plurality of branch structures when a process bias supports fabrication of a respective predetermined dimension associated with the branch structures; and (C) generating, in response to the branch currents, an output indicative of the process bias obtained during fabrication of the layout structure.

Abstract: An apparatus comprising a first circuit, a second circuit, and a logic circuit. The first circuit may be configured to generate one or more first control signals having a first data rate in response to an input signal having a second data rate and a clock signal having the first data rate. The second circuit may be configured to generate one or more second control signals in response to the input signal and the clock signal. The first logic circuit may be configured to generate the clock signal in response to the one or more first control signals, the one or more second control signals and a third control signal.

Abstract: A USB device for communicating data from the device to a USB host is provided. The USB device may have an interrupt or isochronous endpoint for communicating interrupts to the host and a bulk data endpoint for communicating bulk data to the host. The USB device may communicate a signal over the interrupt or isochronous endpoint to the host indicating that the device has bulk data to communicate to the host and may communicate bulk data over the bulk endpoint in response to bulk data requests from the host generated based on the signal over the interrupt or isochronous endpoint.

Abstract: The invention enables a layer of metal to be formed on a substrate with few or no voids formed in the layer, with increased throughput and without raising the temperature of the substrate to a level that may damage the substrate. A layer of metal can be formed on a substrate using a cold deposition step followed by a hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit metal over the entire surface on which the metal layer is to be formed. In the hot deposition step, further metal is deposited while the substrate is rapidly heated to a target temperature. The rapid heating quickly mobilizes the atoms of the deposited metal, making the deposited metal far less susceptible to cusping and voiding than has been the case with previous methods for depositing a metal layer on a substrate that include a cold deposition step followed by a hot deposition step.

Abstract: An architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media that may comprise a first circuit configured to present a first series of data packets having a first bit-width in response to a second series of data packets having a second bit-width and a second circuit configured to present a third series of data packets having said first bit-width in response to said second series of data packets. The first circuit may comprise a buffer circuit configured to hold one or more of the first series of data packets and a packer circuit configured to present the second series of data packets in response to the data packets held in the buffer circuit. The second circuit may comprise an unpacker circuit configured to present the third series of data packets and a buffer circuit configured to hold one or more of the third series of data packets.

Abstract: An apparatus comprising an analog circuit, a passive circuit and a first circuit. The analog circuit may be configured to vary a voltage of an output signal in response to a first signal. The passive circuit may be configured to further vary the voltage. The first circuit may be configured to further vary the voltage. The first circuit generally comprises a parasitic capacitance. The passive circuit and the first circuit are generally coupled in series.

Abstract: An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured generate a first output signal having a first data rate and in response to (i) an input signal having a second data rate and (ii) a clock signal having the second data rate. The second circuit may be configured to generate a second output signal having a third data rate in response to (i) a divided version of the input signal and (ii) the clock signal. The logic circuit may be configured to generate the clock signal in response to (i) the first output signal and (ii) the second output signal.

Abstract: An apparatus for transferring of integrated circuit devices or other devices into and/or out of a plurality of sockets includes at least one guide rod; a presser housing slidingly coupled to the at least one guide rod; a socket presser block movably coupled to the presser housing and a handle assembly. The presser block defines a matrix of cutouts and ribs and is configured to assume a first position in which the presser housing is slideable on the guide rod and a second position in which the matrix of cutouts is aligned with corresponding underlying sockets mounted to a board and in which at least some of the ribs push on the underlying sockets to retract contacts thereof to allow the devices to be transferred into and/or out of the underlying sockets through the cutouts.

Abstract: The present invention provides a method for cleaning particles from a semiconductor topography that has been polished using a fixed-abrasive polishing process by applying a cleaning solution including either (a) an acid and a peroxide or (b) an acid oxidant to the topography. According to an embodiment, a semiconductor topography is polished by a fixed-abrasive process in which the topography is pressed face-down on a rotating polishing pad having particles embedded in the pad while a liquid absent of particulate matter is dispensed onto the pad. The particles may include, e.g., cerium oxide, cerium dioxide, &agr;alumina, &ggr;alumina, silicon dioxide, titanium oxide, chromium oxide, or zirconium oxide. A cleaning solution comprising either (a) an acid and a peroxide, e.g., hydrogen peroxide, or (b) an acid oxidant is applied to the semiconductor topography after the polishing process is completed.

Abstract: According to one embodiment (500), a method of depositing an insulating layer to fill constrained spaces on an integrated circuit is disclosed. Gate structures are formed that include sidewall structures (502 and 504). An insulating layer may then be deposited over the gate structures (506). An insulating layer may be deposited by high density plasma CVD to create a silicon dioxide layer with relatively high levels of phosphorous. An insulating layer formed in this manner may fill constrained spaces and may not include a following reflow step. This may allow for a smaller thermal budget and may reduce process complexity and/or cycle time. In the event the insulating layer is substantially phosphosilicate glass (PSG), the formation of a “cap” layer of undoped silicon oxide may be avoided. Without a cap layer, contact holes may be etched through an insulating layer with a single etch step. This may also reduce process complexity and/or cycle time.

Abstract: A circuit and method comprising a memory array and a plurality of address circuits. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The plurality of address circuits may each be configured to generate one of said internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal.

Abstract: An apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first control signal, (ii) a second control signal and (iii) the adjustment signal in response to a rate of an input signal.

Abstract: A current source and a load circuit. The oscillator circuit may be configured to present an output signal having a frequency in response to (i) a current, (ii) a load, and (iii) an input signal. The current source may be configured to generate the current in response to one or more first control signals. The load circuit may be configured to generate the load in response to one or more second control signals.

Abstract: A design, layout, schematic, netlist, abstract or other equivalent circuit representations for a memory that may have redundant circuitry may be generated from a set of user inputs acquired through a graphical user interface. Based on the user inputs one or more leaf cells is/are generated. Then using the leaf cells, a design database for the layout is generated from the user inputs. The design database reflects physical hierarchies of the layout and may include redundancy circuitry within a data and/or address path, parallel to a non-redundant data and/or address path within the layout. The above-mentioned parameters described by the user inputs may include an array size, a defect rate, and/or a leaf cell design, layout or schematic. This scheme may be embodied as a set of computer-readable instructions, for example to be executed by a computer system.