Abstract: Water vapor plasma etching of metal surfaces facilitates removal of organic residues over metal surfaces. By plasma etching metal surfaces covered with an organic material, such as photoresist, in an atmosphere in which the water vapor to O2 ratio exceeds 5:3 (such as about 5:1, for example), superior organic material removal results are observed, particularly over relatively wide metal surfaces. The duration of the water vapor plasma etch also may be increased, relative to conventional organic material-removing processes. The effectiveness of the high vapor etch according to the present invention allows the elimination of a subsequent dry organic material stripping step, reducing processing time and cost while increasing yields.

Abstract: A voltage regulator includes a static regulator that provides a static regulated supply output as a reference input to a dynamic regulator to provide a regulated supply voltage. In one embodiment, multiple dynamic regulators are connected to the static regulated supply output of the static regulator. The one or more dynamic regulators dynamically detect when the regulated supply voltage is loaded below a predetermined reference level, and provide extra current in response to prevent the regulated supply voltage from drooping. Since the static regulator is capable of handling large average currents, the dynamic regulator circuit can be smaller than a typical dynamic regulator for an equivalent load. Furthermore, since the dynamic regulator provides transient current requirements, the size of the static regulator may be likewise smaller in size than a typical static regulator for an equivalent load.

Abstract: An electrostatic or mechanical chuck assembly includes gas inlets only in an annulus-shaped peripheral portion and not in the central region of the chuck. The gas inlets are in fluid communication with one or more gas conduits and supply of the backside of a workpiece, such as a semiconductor wafer, with inert coolant gas or gases. The gas or gases supplied only to the peripheral region of the chuck effectively cool the central region of the chuck by at least two physical mechanisms, including the thermal conduction through the workpiece and diffusion of the gas or gases in the interstitial space(s) between the somewhat irregular facing surfaces of the chuck and of the backside of the workpiece.

Abstract: A routing architecture which includes a plurality of switching elements grouped so as to provide one or more outputs for a plurality of inputs, wherein the grouping represents a hierarchy of selection levels. The routing architecture may be configured such that at each of the selection levels fewer outputs are provided than inputs are received. The selection levels may be implemented using one or more multiplexers at each of the levels. The routing architecture may be embodied in a programmable logic device which may also include a number of logic blocks. Each of the logic blocks may be coupled to receive at least one of the outputs of the routing architecture and the programmable logic device may be configured so that a subset of the plurality of inputs to the routing architecture are provided by one or more of the logic blocks.

Abstract: A programmable logic device comprising one or more first stages and one or more second stages. The one or more first stages may comprise one or more gates of a first type each having a first number of inputs. The one or more second stages may comprise one or more gates of a second type each having a second number of inputs, wherein said first and second stages are interlaced.

Abstract: A circuit including a plurality of first calibration circuits, a second circuit and a third circuit. The plurality of calibration circuits may each be configured to present a calibration signal. The second circuit may be configured to select one of the calibration signals in response to a plurality of configuration signals. The third circuit may be configured to generate a control signal in response to (i) a reference signal and (ii) the selected calibration signal.

Abstract: A microprogrammable microprocessor that stores microprogramming instruction sets in a dual ROM configuration enhancing reusability of subroutine operations common between two or more instructions. A first ROM contains a look up table identifying the subroutine(s) utilized by each instruction. The second ROM contains the subroutines needed to implement the required operations for each instruction. The dual ROM microprogrammable microprocessor is used in a Universal Serial Bus microcontroller development system having a microprocessor, control circuit, and an interface to USB bus. The microprocessor system state and I/O registers are mapped to a system bus sharing the same lines with a control circuit. The control circuit provides an RS-232 interface to an attached computing device able to write and read data words to the system bus, thereby to control the microprocessor and associated hardware by setting the system state and writing/reading data from RAM.

Abstract: A circuit and/or method comprising an oscillator circuit, a pulse detection circuit and a control circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The pulse detection circuit may be configured to generate a detect signal in response to the output signal. The control circuit may be configured to generate the second control signal in response to said detect signal.

Abstract: A circuit comprising a first circuit and a state machine. The first circuit may be configured to generate a plurality of state inputs in response to (i) a first clock signal, (ii) a second clock signal delayed from the first clock signal, and (iii) a data signal. The state machine may be configured to generate a pump up signal and a pump down signal in response to (i) said data signal and (ii) a plurality of quadrants defined by a number of possible combinations of the state inputs. The state machine may be further configured to transition between any of the quadrants.

Abstract: An apparatus for synchronizing a clock signal to a data signal. The apparatus comprises a detector and a control circuit. The detector may be configured to produce a value representing a position of an edge of said data signal based upon a state of said clock signal. The control circuit may be configured to adjust the clock signal based upon the value.

Abstract: A memory circuit that allows for short retransmit recovery times by implementing a read cache memory in a FIFO device. A circuit comprising a memory array, a cache memory and a logic circuit. The memory array includes a read pointer, a write pointer and a plurality of memory rows. The cache memory is configured to store one or more memory data bits. The logic circuit is further configured to control the output of the circuit by presenting either (i) an output from the memory array or (ii) an output from the cache memory.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more enable signals in response to a first control signal and a clock signal. The second circuit may be configured to generate an output signal in response to the one or more enable signals and the clock signal. The first circuit is configured to sample a frequency of the clock signal.

Abstract: A circuit structure combines an integrated circuit with a passive circuit element formed within a grid-array substrate. Formation of the circuit structure includes forming a passive circuit element within one or more conductive layers of a grid-array substrate such as may be used for packaging of integrated circuits. A pair of terminals of the passive circuit element is coupled to a pair of passive element contact pads within a processed surface of the integrated circuit, thereby connecting the integrated circuit to the grid-array substrate. The same grid-array substrate may be used for formation of the passive circuit element and for packaging of the integrated circuit. In some embodiments the lateral extent of the integrated circuit overlaps the lateral extent of the passive circuit element. Alternatively, the passive circuit element may be laterally displaced from the integrated circuit.

Abstract: An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.

Abstract: The present invention advantageously provides a method and apparatus for polishing a semiconductor topography by applying a liquid which is void of particles between the topography and an abrasive polishing pad surface. The semiconductor topography is rotated relative to the polishing surface to polish elevationally raised regions of the topography. The particles are fixed within the polishing surface which may comprise a polymeric material. In one embodiment, the liquid may comprise water diluted with acid. If the liquid is adjusted to have a pH between 6.0 and 7.0, the polishing process may be used to remove a silicon dioxide layer from the topography at a faster rate than a silicon nitride layer residing beneath the oxide layer. Alternately, a metal may be selectively removed from above an oxide layer if the polishing liquid has a pH between 2.0 and 5.0. In another embodiment, the liquid may be deionized water. The water does not react with the material being polished.

Abstract: A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a recall operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section.

Abstract: A memory device includes an address pipeline configured to receive a write address at a first time and to provide the write address to a memory array at a second time, corresponding to a time when write data associated with the write address is available to be written to the array. The address pipeline may include a series of registers arranged to receive the write address and to provide the write address to the memory array. In addition, the memory device may include a comparator coupled to the address pipeline. The comparator is configured to compare the write address to another address (e.g., a read address) received at the memory device. A bypass path to the array may be provided for read addresses received at the memory device. A data pipeline is configured to receive data destined for the memory device and to provide the data to the memory array. The data pipeline may include a data bypass path which does not include the memory array.

Abstract: A semiconductor (preferably a CMOS) device having one or more latch-up inhibitor diffusion regions. The latch-up inhibitor regions are adjacent to complementary P-channel and N-channel transistors, and typically function to inhibit or prevent latch-up, without increasing the die size of the device.

Abstract: A programmable interconnect matrix (PIM) design, layout, schematic, netlist, abstract or other equivalent circuit representation (hereinafter “layout”) is hierarchically generated by selecting one or more PIM layout tiles from a plurality of different PIM layout tiles, and automatically compiling a plurality of the selected PIM layout tiles into a PIM layout. In some cases, the PIM layout tiles can be heterogeneous. Generally, the PIM layout includes a PIM array having one of a plurality of different sizes (e.g., n rows by m columns, n and m>1). In other embodiments, a PIM connection scheme is generated by automatically compiling a plurality of PIM layout tiles into a PIM layout, then programming interconnects of the PIM according to a mapping table specifying desired interconnections. This scheme may include generating the mapping table with software configured to optimize connections and/or routability and/or automatically generating a PIM layout database from the PIM connection scheme.

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.