Abstract: A circuit comprising an oscillator, a reference path, and a feedback path. The oscillator may have a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output. The reference path may provide the reference signal from a reference clock input. The feedback path may provide the feedback signal from the oscillator loop output. At least one of the reference path and the feedback path comprises a programmable delay circuit.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal in response to one or more first input signals. The second circuit may be configured to generate a second output signal in response to one or more second input signals. The first and second output signals may be presented to a bond pad.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to drive a first bus in response to a first control signal. The second circuit may be configured to control a voltage of the first bus in response to the first control signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) generate one or more first parallel data signals in response to a first serial data stream and a first control signal and (ii) generate a second serial data stream in response to one or more second parallel data signals and a second control signal. The second circuit may be configured to write the one or more first parallel data signals to and read the one or more second parallel data signals from an array of storage elements in response to one or more control signals.

Abstract: A circuit including a counter, a state machine and an update circuit. The counter may be configured to present a first control signal and a second control signal in response to a reset signal and a third control signal. The state machine may be configured to generate a select signal in response to (i) the reset signal, (ii) the first control signal and (iii) the second control signal. The update circuit may be configured to generate a fourth control signal in response to the select signal.

Abstract: According to one embodiment (100), a method of manufacturing a semiconductor device may include forming diffusion regions in a substrate with a gate, first spacer, and second spacer as a diffusion mask (102). A second spacer may then be removed (104) prior to the formation of an interlayer dielectric. An interlayer dielectric may then be formed (106) over a gate structure and first spacer. A contact hole may then be etched through the interlayer dielectric that is self-aligned with the gate (108).

Abstract: A non-volatile memory cell comprising a first transistor and a second transistor. The first transistor may be configured to receive an input and a first voltage. The second transistor may be configured to receive said input and a second voltage. The first and second transistors are generally coupled to an output.

Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.

Abstract: IC fabrication employs the deposition of aluminum as a metallization layer. Frequently, the aluminum is doped with copper in small amounts to improve electric properties. Low temperature deposition of these layers is preferred to ensure the proper microstructure and surface roughness. Low temperature deposition (below about 300° C.) results in the formation of copper precipitates which can be difficult to remove. Annealing the layer formed, either prior to, or after formation of capping layers and additional layers thereon, drives the copper precipitate back into solution, permitting small dimension fabrication.

Abstract: A microcontroller including a system bus; a microprocessor coupled to the system bus and configured to transfer data and control signals over the system bus; a memory device coupled to the microprocessor and mapped to the system bus and configured to store microprogram instructions for execution by the microprocessor; a controller coupled to the system bus and configured to transfer data and control signals to the microprocessor over the system bus; a host interface coupled to the system bus and configured to interface to a host computer and receive the data and the control signals over the system bus from the microprocessor; and an I/O interface coupled to the system bus and configured to interface to at least one I/O device and receive the data and the control signals over the system bus from the microprocessor.

Abstract: A circuit and method for controlling a wordline and/or stabilizing a memory cell comprising a first circuit and a second circuit. The first circuit may be configured to generate a control signal in response to (i) a select signal and (i) an equalization signal. The second may be configured to generate an output signal in response to (i) the control signal and (ii) a global wordline signal. The output signal may be presented to one or more memory cells of a memory array.

Abstract: A lead frame includes a first side rail, a second side rail spaced apart from the first side rail, a center rail disposed between the first side rail and the second side rail, and a plurality of package locations. Each package location includes a first and a second die attach paddle. The first die attach paddle supports a first side of a semiconductor die and is coupled only to the first side rail or to the second side rail. The second die attach paddle supports a second side of the semiconductor die and is coupled only to the center rail. The first and second die attach paddles are separate and unconnected to each other and may be generally circular in shape. An aggregate surface area of the first and second paddles may be less than about 25 percent of a surface area of the semiconductor die.

Abstract: A device generally comprising a memory array and a burst sequence generator. The memory array may be configured to store data. The burst sequence generator may be configured to generate a burst sequence in response to address information received by the device. The burst sequence may be configured to identify a plurality of locations for storing data in the memory array. The device may have a maximum operating current of 50 milliamps and/or a maximum standby current of about 25 microamps.

Abstract: A circuit comprising a first and a second circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a first input signal and (ii) an enable signal. The first control signal generally matches the second control signal. The second circuit may be configured to generate a third control signal and a fourth control signal in response to (i) a second input signal and (ii) the enable signal. The third control signal generally matches the fourth control signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of clock signals each in response to (i) one or more control inputs and (ii) one or more of a plurality of phase timing elements. The second circuit may be configured to generate the plurality of phase timing elements.

Abstract: A memory device (e.g., an SRAM) is configurable to be operated in an asynchronous or a synchronous mode in accordance with a value stored in a control register thereof. In addition to asynchronous and synchronous operating modes, additional features such burst mode operations, including asynchronous burst mode operations and/or synchronous burst mode operations (e.g., linear sequential and/or interleaved burst operations); the number of pipeline stages of an output path of the SRAM; and/or the number of data hold cycles for synchronous operation of the SRAM are configurable in accordance with additional values stored in the control register.

Abstract: An asynchronous memory device includes parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the first output signals and to produce second output signals indicative of logic states of the first output signals therefrom. The parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time. The plurality of cells tested may include a redundant cell of the device. Such redundancy is transparent to the test circuitry.

Abstract: An apparatus comprising a detector circuit and a first circuit. The detector circuit may be configured to (i) provide a bias voltage and (ii) generate a plurality of first signals and a plurality of second signals. The first circuit may be configured to (a) present (i) the bias voltage and (ii) a differential signal in response to the plurality of first signals and the plurality of second signals and (b) control (i) one or more of the plurality of first signals and (ii) one or more of the plurality of second signals.

Abstract: A method for conditioning a plasma etch chamber is presented. A plasma etch chamber is provided, which preferably includes a chuck for supporting a topography. A conditioning process may be performed in the etch chamber. The conditioning process preferably includes positioning a cover topography on or above the chuck. A conditioning feed gas containing (hydro)halocarbons may be introduced into the chamber. A conditioning plasma may be generated from the conditioning feed gas for a conditioning time. Immediately after generating the conditioning plasma is complete, the overall thickness of the cover topography is preferably at least as great as immediately before generating the conditioning plasma. By performing a conditioning process in such a manner, the total cost and complexity of the conditioning process may be reduced.

Abstract: A circuit for addressing leakage. The circuit may have a variable supply stage having an active load in parallel with a switch transistor where the active load and the switch transistor are coupled to a decoupling capacitor. The circuit may also have a leakage detect stage having a leak device coupled to a critical node. An embodiment of the circuit may have a supply node; an input node; an output node; a buffer stage where the buffer stage supply node is coupled to a variable supply stage output, the buffer stage input is coupled to the input node and the buffer stage output is coupled to the output node; a leakage detect stage where the leakage detect stage supply node is coupled to the supply node and the leakage detect stage input is coupled to the input node; and a variable supply stage where the variable supply stage supply node is coupled to the supply node and the variable supply stage input is coupled to the leakage detect stage output.