Abstract: A design, layout, schematic, netlist, abstract or other equivalent circuit representations for a memory that may have redundant circuitry may be generated from a set of user inputs acquired through a graphical user interface. Based on the user inputs one or more leaf cells is/are generated. Then using the leaf cells, a design database for the layout is generated from the user inputs. The design database reflects physical hierarchies of the layout and may include redundancy circuitry within a data and/or address path, parallel to a non-redundant data and/or address path within the layout. The above-mentioned parameters described by the user inputs may include an array size, a defect rate, and/or a leaf cell design, layout or schematic. This scheme may be embodied as a set of computer-readable instructions, for example to be executed by a computer system.

Abstract: A circuit including an address bus providing random addresses for a random access memory array, and a register configured to receive, store or transfer (i) a first random address from the address bus in response to a first periodic signal transition and (ii) a second random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle, and are preferably complementary to each other.

Abstract: A circuit and method comprising a multiplexer circuit, a select circuit and a buffer circuit. The multiplexer circuit may be configured to present a data bit in response to a first control signal. The select circuit may be configured to generate one or more first outputs in response to (i) the data bit and (ii) one or more first select signals. The buffer circuit may be configured to present one or more second outputs on a data bus in response to (i) the one or more first outputs and (ii) one or more second control signals. One of the second outputs may have a data state and the rest of the second outputs may have a high impedance state. The first and select signals may be generated by a logic circuit.

Abstract: An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii) a high-Z state.

Abstract: A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.

Abstract: A timing crystal oscillator circuit that may be tuned after production. The circuit generally comprises a microprocessor configured to present one or more control signals, one or more load devices that may be activated in response to the control signals and a crystal oscillator for presenting an output signal having a frequency which is generally dependent on the number of load devices activated.

Abstract: An input buffer having a stable trip point over at least process skew and supply voltage variations includes a first inverter stage; a second inverter stage; and an arrangement for compensating for process skew and supply voltage variations. The compensating arrangement is disposed both in the pull-up and pull-down paths, and increases the conductivity of the pull-up path and decreases the conductivity of the pull-down path when the DC trip point of the input buffer falls below nominal. The compensating arrangement also decreases the conductivity of the pull-up path and increases the conductivity of the pull-down path when the DC trip point rises above nominal. The compensating arrangement may include at least one device disposed in each of the pull-up and pull-down paths. The conductivity of these devices may then be controlled by a reference signal that swings about the DC trip point responsive to at least process skew corners and variations in supply voltage.

Abstract: A circuit comprising an oscillator configured to generate a periodic signal in response to (i) control signal and (ii) a current. The current may be varied independently of the control signal. In one example, the oscillator may generate the periodic signal in further response to a second current that may vary in response to the control signal. In another example, the oscillator may be used in a phase-locked loop circuit.

Abstract: The invention enables extension of the useful life of a chemical bath used to process a substrate. The invention can employ an improved rinsing method that removes defects from a substrate with sufficient effectiveness to obtain acceptable defect levels even as the quality (e.g., composition and/or contaminant level) of the chemical bath degrades over time such that substrates that are immersed in the bath accumulate more defects than can be adequately removed by previous rinsing methods. For example, the invention can enable a stagnant chemical bath to be used for a period greater than 24 hours without replacing the bath fluid. Similarly, it is expected that use of the invention can enable a recirculated chemical bath to be used for a period greater than 48 hours without replacing the bath fluid.

Abstract: A circuit and method configured to generate a variable impedance. The circuit may comprise a voltage controlled resistor configured to generate the variable impedance in response to (i) a first transistor configured to receive a first control signal and (ii) a bias transistor configured to receive a bias signal. In one example, the variable impedance may be generated in further response to a clamp transistor.

Abstract: The present invention integrates a phase lock loop (PLL) with a programmable logic device (PLD) to realize a flexible PLD with a variety of clocking options. The present invention generates multiple clock frequencies internally to a programmable logic device using a single reference clock input. The programmer can dynamically change the functionality of the programmable logic device. As a result, a “virtual hardware device” is realized. The ability to change the frequency of operation also dynamically offers a tremendous advantage to users of reconfigurable computing.

Abstract: A delay generation circuit comprising (i) a circuit configured to generate a reference clock signal having a period, (ii) a divide circuit and (iii) an output circuit. The divide circuit may be configured to generate a first divided clock signal and a second divided clock signal in response to said reference clock signal. The output circuit may be configured to generate (i) a first output clock signal and (ii) a second output clock signal in response to (i) the first and second divided clock signals and (ii) the reference clock signal. The second output clock signal may have a delay with respect to the first output clock signal. The delay may be (i) a multiple of or (ii) a fraction of the period of the reference clock signal.

Abstract: An apparatus comprising a first circuit and a deserializer circuit. The first circuit may be configured to present a clock signal and a data signal having a second data rate in response to an input signal having a first data rate. The deserializer circuit may be configured to generate an output signal in response to (i) the clock signal, (ii) the data signal and (iii) one or more select signals.

Abstract: The invention relates to a voltage reference source used to control an overvoltage tolerant input/output buffer for a mixed voltage bus system. The voltage source comprises a voltage tracking circuit having a first input receiving a variable voltage. and a second input receiving a reference voltage. the voltage tracking circuit being adapted to generate an output voltage in response to the difference between the variable voltage and the reference voltage. wherein where the variable voltage is less than the reference voltage. the output voltage is held at substantially zero volts. When the variable voltage exceeds the reference voltage. the output tracks the voltage at the variable voltage input.

Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.

Abstract: A random access memory with a read port, a write port, a read/write control signal configured to control data transfer operations at the read port and/or the write port on both rising and falling transitions, and a first random access memory array configured to store and/or retrieve data at a first random address in the first random access memory array defined by one or more signals on a write address bus and/or a read address bus. One preferred embodiment further includes a write data register storing or latching data in response to a first transition of the read/write control signal, and the array storing data in response to a second transition of the read/write control signal. Other preferred embodiments further include an n·m-bits-wide input data bus coupling a set of data inputs to the write data register, and/or an n·m-bits-wide output data bus coupling the read data register to a set of data outputs, where n and m are each independently an integer >2.

Abstract: A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

Abstract: A random access memory with a data input bus, a data output bus, a random access memory array configured to transfer data to random write addresses and from random read addresses in the random access memory array, an address bus providing the random read addresses and the random write addresses, and a first periodic signal configured to control data transfer operations (i) to the random access memory array in response to a first transition of the periodic signal and (ii) from the random access memory array in response to a second transition of the periodic signal, wherein the second transition of the periodic signal is complementary to the first transition of the periodic signal. One preferred embodiment further includes circuitry operable to write data into and read data from the random access memory array. Other preferred embodiments further include a write data register and/or a read data register. In a further embodiment, each of the data input bus and the data output bus is unidirectional.

Abstract: The present invention advantageously provides a method for forming a nitride sidewall spacer having a relatively thin upper portion and a lower portion that increases in lateral thickness as it substantially tapers toward an underlying surface. In an embodiment, nitride sidewall spacers having this shape are formed upon the opposed sidewall surfaces of gate conductors which are dielectrically spaced above a semiconductor substrate. The upper portion of each spacer is bounded by a substantially vertical upper outer surface while the lower portion is bounded by a lower outer surface which is angled away from the upper outer surface. A unitary source/drain implant may be forwarded into the substrate to form graded junctions. The implant is self-aligned to the upper outer surfaces of the nitride spacers. As such, the graded junctions are displaced laterally from the gate conductors by a distance which is dictated by the lateral thickness of the upper portion of each spacer.

Abstract: An apparatus comprising a memory and a logic circuit. The memory may comprise a plurality of storage elements configured to read and write data in response to a first internal address signal and a second internal address signal. The logic circuit may be configured to generate either (i) the first and the second internal address signals when accessing one of the storage elements for a read or a write operation or (ii) the first internal address signal when accessing one of the storage elements for a read refresh operation.