Abstract: A system for reconfiguring a peripheral device having a first configuration connected by a computer bus and a port to a host computer. The system comprises a first circuit and a second circuit. The first circuit may be configured to download information for a second configuration from the host computer into the peripheral device over the computer bus. The second circuit may be configured to electronically simulate, over the computer bus, a physical disconnection and reconnection of the peripheral device to reconfigure the peripheral device to the second configuration.

Abstract: A circuit comprising a memory array, a driver circuit, and a logic circuit. The memory array may have a plurality of memory cells arranged in a plurality of rows. Each cell may be configured to read and write data. The driver circuit may be configured to present a plurality of word line signals in response to a decoded row signal and a disable signal. The logic circuit may be configured to generate the disable signal in response to (i) one or more programmed redundant row signals and (ii) a decoded group signal.

Abstract: A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) a global signal. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of the enable signals generally reduces current consumption in the memory array.

Abstract: A circuit and method for providing a fast transitioning output buffer that may be configured to operate using either a 3 volt or 5 volt supply voltage. The pullup behaves similarly to a MOS diode, but the circuit lowers the gate voltage on a pullup while the output is being pulled up. The circuit does not affect the final pullup voltage. As a result, a single PMOS device may be used as a pullup device that does not generally require an increased size to support a high operating voltage.

Abstract: A method of generating write control signals insensitive to glitches on a data input signal comprising the steps of (A) enabling a write of a first or second value in response to a data input transition, (B) holding in a ready state until the data input is stable and (C) writing stable data into a memory array.

Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width wmux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width wmux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.

Abstract: An apparatus comprising a first memory and a second memory. The first memory may be configured read and write words from a data stream comprising a plurality of words in response to (i) a first read enable signal and (ii) a first write enable signal. The second memory may be configured to read and write words from the data stream in response to (i) a second read enable signal and (ii) a second write enable signal. The first and second memories may be configured to read and write alternate words of the data stream.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first signal and a second signal in response to a pump down signal and (ii) a third signal and a fourth signal in response to (i) a pump up signal. The second circuit may be configured to generate (a) a first control signal in response to (i) the first signal and (ii) the third signal and (b) a second control signal in response to (i) the second signal and (ii) the fourth signal.

Abstract: A circuit comprising a plurality of input devices, a plurality of select devices and a selector device. The plurality of inputs may each be configured to receive an input. The plurality of select devices may each be configured to present an output in response (i) one of said plurality of inputs and (ii) one of a plurality of select signals. The selector device may be configured to present the plurality of select signals, where only one of the select signals is active at a time.

Abstract: A product-term allocation architecture for a programmable device, comprising a plurality of logic gate sections and a fully rotatable, programmable OR-type array. A first one of the logic gate sections may comprise a first plurality of fixed logic gates. Each of the first plurality of fixed logic gates may have m inputs, m being an integer of at least one. A second one of the logic gate sections may comprise a second plurality of fixed logic gates. Each of the second plurality of fixed logic gates having n inputs, n being an integer of at least two and being different from m. The plurality of logic gate sections may be configured to provide p outputs, p being an integer equal to or greater than the total number of the fixed logic gates and less than the total number of fixed logic gate inputs. The fully rotatable, programmable OR-type array may receive the p outputs and may be configured to generate a plurality of array outputs.

Abstract: A circuit comprising an output circuit, an adjustment circuit and a detect circuit. The output circuit may be configured to present a first and second output in response to (i) a first and second control signal and (ii) an input signal. The slew rate adjustor circuit may be configured to present the first and second control signals in response to a third control signal. The detect circuit may be configured to present the third control signal in response to the first and second output signals. The slew rate adjuster circuit may dynamically adjust a slew rate of the first and second output signals to minimize common-mode changes.

Abstract: The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform.

Abstract: An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first current in response to a first input signal. The second circuit may be configured to generate a second current in response to a second input signal. The third circuit may be configured to present a first pulse of current at a first output or a second pulse of current at a second output in response to the first and second currents.

Abstract: The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.

Abstract: An output buffer includes a continuously variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as a pullup/pulldown transistor, for receiving an input signal and generating an output signal on an output node in response thereto. In addition, the buffer includes a control circuit and a low-impedance driver in an electrical communication with the output node and, preferably, disposed in parallel with at least one of the pullup and/or pulldown transistors. The control circuit receives the output node voltage and generates a control signal on a control node that varies according to the magnitude of the output node voltage. The driver is biased by the control signal and has a conductivity that varies according to the control signal. The variations in the conductivity are operative to adjust the output impedance of the buffer.

Abstract: A circuit comprising a pump-up circuit and a pump-down circuit. The pump-up circuit may be configured to generate a pump-up signal in response to (i) a data signal and a clock signal. The pump-down circuit may be configured to generate a pump-down signal in response to (i) the data signal, (ii) the clock signal, and (iii) a quadrature of the clock signal.

Abstract: A system and method for interfacing between an input/output system, that includes a local computer bus, a processor connected to the local computer bus and an interface to a computer system bus, and a computer system having a main memory is provided. The system includes a memory system with a memory controller that controls access and storage of data. The system may initiate sequential or burst ordered blocks of data over the computer bus from the computer system in anticipation of random access requests for data by the processor. A system and method for interfacing a plurality of processors to a computer system having a system bus and a main memory is also provided.

Abstract: An I/O interface circuit which is capable of tolerating the application of an overvoltage condition to a corresponding I/O pad but which also has a relatively low trip point voltage includes an overvoltage detection circuit configured to have a trip point at a first voltage provided by a voltage divider circuit. The voltage divider circuit may include a pair of transistors coupled in series between a voltage source having a second voltage and ground. In such cases, the first voltage may be approximately equal to the difference between the second voltage and a threshold voltage of one of the pair of transistors. Alternatively, the voltage divider circuit may include a NAND gate having an output coupled to the overvoltage detection circuit and an input coupled to receive a second voltage. The second voltage may be determined by a voltage at an I/O pad of the I/O interface and one or more diodes coupled between the I/O pad and the NAND gate.

Abstract: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.