Abstract: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

Abstract: An I/O interface circuit which is capable of tolerating the application of an overvoltage condition to a corresponding I/O pad but which also has a relatively low trip point voltage includes an overvoltage detection circuit configured to have a trip point at a first voltage provided by a voltage divider circuit. The voltage divider circuit may include a pair of transistors coupled in series between a voltage source having a second voltage and ground. In such cases, the first voltage may be approximately equal to the difference between the second voltage and a threshold voltage of one of the pair of transistors. Alternatively, the voltage divider circuit may include a NAND gate having an output coupled to the overvoltage detection circuit and an input coupled to receive a second voltage. The second voltage may be determined by a voltage at an I/O pad of the I/O interface and one or more diodes coupled between the I/O pad and the NAND gate.

Abstract: A system and method for interfacing between an input/output system, that includes a local computer bus, a processor connected to the local computer bus and an interface to a computer system bus, and a computer system having a main memory is provided. The system includes a memory system with a memory controller that controls access and storage of data. The system may initiate sequential or burst ordered blocks of data over the computer bus from the computer system in anticipation of random access requests for data by the processor. A system and method for interfacing a plurality of processors to a computer system having a system bus and a main memory is also provided.

Abstract: An apparatus comprising a memory section and a first circuit. The memory section may be configured to present a first output in response to (i) a first clock signal, (ii) a second clock signal, (iii) an input pulse and (iv) the first output. The first circuit may be configured to generate a second output in response to (i) the first output and (ii) the second clock signal, where the second output may comprise a pulse having a width equal to a period of the second clock signal. In one example, an input circuit may be configured to present the first output to the memory section in response to the input pulse and a first feedback of the output.

Abstract: Architecture, circuitry, and methods are provided for operating a high speed, volatile programmable logic integrated circuit using back-up non-volatile memory cells configured on an integrated circuit separate from the programmable logic integrated circuit. The lower density non-volatile memory cells can be formed on an integrated circuit using fabrication steps similar to those used to form, e.g., EEPROM devices or, more specifically, flash EEPROM devices. The programmable logic integrated circuit includes high density, volatile memory cells integrated with high speed, low density configurable CMOS-based logic. By using two separate processing technologies on two separate and distinct monolithic substrates, and interconnecting the separate integrated circuits on a singular monolithic substrate, the advantages of non-volatility can be combined with a high speed programmable circuit.

Abstract: According to one embodiment (100), a method of forming contacts may include forming structures that include sidewalls (102). A first insulating layer can be deposited (104). A second insulating layer can then be deposited over the first insulating layer (106). The second insulating layer can be patterned to form a hard etch mask (108). Contact holes can be etched through the second insulating layer using the hard etch mask as a contact hole etch mask (110). A second insulating layer can have a dielectric constant that is low with respect to other hard etch mask materials, such as silicon nitride. A hard etch mask formed from a second insulating layer can result in contact holes having lower aspect ratios than conventional approaches.

Abstract: A circuit comprising an oscillator configured to provide a first output signal in response to one or more input signals. A divider circuit may be configured to receive the first output signal of the oscillator circuit and to present a signal having a second frequency at a second output. A frequency comparator circuit may receive the second output signal and an external signal having a third frequency and may present a third output signal representing control information. A processor circuit may be coupled to the oscillator circuit, the divider circuit and the comparator circuit. The processor circuit may control the frequency of oscillation of the first output.

Abstract: An apparatus comprising a first circuit and a clock circuit. The first circuit may be configured to generate an output signal and a re-timed data signal in response to (i) a data input signal, (ii) a first clock signal and (iii) a second clock signal. The clock circuit may be configured to generate the first and second clock signals in response to the output signal.

Abstract: A programmable device architecture that may improve functionality over look-up table based or product-term based programmable logic devices and that may provide for the efficient implementation of user-programmable logic designs resulting in implementations that may require less area and may provide increased performance. A product-term array (either fully or partially populated) may be placed in front of a number of LUT-based macrocells, utilizing the available routing wires as wordlines to form the product terms. The present invention takes advantage of existing routing to do more than just route signals from one point to another by allowing logic to be implemented in the same die area. The result is logic implementations that may require fewer total macrocells, fewer levels of macrocells, and fewer point-to-point nets (because logic density increases). The present invention may apply to FPGAs comprising an array of macrocells and to FPGAs comprising an array of clustered macrocells.

Abstract: An internal combustion engine comprising an engine block having two opposed guide slots on an interior surface. The guide slots may be parallel to the direction of movement of the engine pistons. At least one pair of cylinders may be formed in the engine block. The pistons may each be moving in a linear direction perpendicular to the inside of a respective one of the cylinders in response to energy forces in a respective chamber positioned at one end of each cylinder.

Abstract: An integrated circuit, a programming mechanism and a method are provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limits against which the test results can be compared may also be programmed into the integrated circuit. The test outcomes of various test operations, test results of various test parameters and test limits of the same or dissimilar test parameters are stored in separate non-volatile storage locations attributed to the integrated circuit.

Abstract: A method of forming non-volatile memory (e.g., an EEPROM device) and a CMOS device (e.g., a RAM), on a single die or chip, and a structure formed by the method. In one embodiment, the control gate of the storage transistor as well as the isolation gate of the isolation transistor may be formed during the same manufacturing process step, and thus may be formed of the same gate poly material and may have similar thickness.

Abstract: A circuit comprising a plurality of input devices, a plurality of de-select devices and a selector device. The plurality of input devices may each be configured to receive an input signal. The plurality of de-select devices may each be configured to present an output in response (i) one of the plurality of inputs and (ii) one of a plurality of de-select signals. The selector device may be configured to present the plurality of de-select signals. In general, all but one of the de-select signals is active at a time.

Abstract: A logic block in a product-term based programmable device comprising a first logic gate, a second logic gate, a macrocell and a multiplexer. The first logic gate may be configured to generate a first output in response to a logical combination of a first number of product terms. The second logic gate may be configured to generate a second output in response to a logical combination of a second number of product terms. The macrocell may be configured to generate a third output in response to the second output. The multiplexer may be configured to select an output of the device in response to (i) the first output or (ii) the third output. The first number of product terms may be a subset of the second number of product terms.

Abstract: The present invention advantageously provides a method and apparatus for polishing a semiconductor topography by applying a liquid which is void of particles between the topography and an abrasive polishing pad surface. The semiconductor topography is rotated relative to the polishing surface to polish elevationally raised regions of the topography. The particles are fixed within the polishing surface which may comprise a polymeric material. In one embodiment, the liquid may comprise water diluted with acid. If the liquid is adjusted to have a pH between 6.0 and 7.0, the polishing process may be used to remove a silicon dioxide layer from the topography at a faster rate than a silicon nitride layer residing beneath the oxide layer. Alternately, a metal may be selectively removed from above an oxide layer if the polishing liquid has a pH between 2.0 and 5.0. In another embodiment, the liquid may be deionized water. The water does not react with the material being polished.

Abstract: A macrocell for a programmable logic device includes a carry generator for generating a carry input to the macrocell, the carry generator having an inverting input and at least one non-inverting input. A carry decoupler controls the carry generator and allows any macrocell to be decoupled from a next adjacent macrocell. An XOR gate having a first input is coupled to the output of the carry generator and a second input thereof is connected to a logic input to the macrocell. A register is coupled to the output of the XOR gate. A macrocell output selector includes a first input coupled to an output of the register and a second input coupled to the output of the XOR gate.

Abstract: A circular product term allocator configured to provide connections for product term signals to macrocells of a programmable logic device is provided. The circular product term allocator may provide such connections through a logic OR function. Alternatively, a homogeneous product term allocator may be configured to provide connections for product term signals to macrocells of a programmable logic device. The homogeneous product term allocator may be configured to provide each of the product term signals to an equal number of macrocells. In yet another embodiment, a programmable logic device includes a plurality of macrocells and a product term allocator configured to provide an equal number of product term signals to each of the macrocells. In yet a further embodiment, a method of distributing product terms in a programmable logic device is accomplished by configuring a product term allocator to provide an equal number of product terms, but fewer than all of the product terms, to each of the macrocells.

Abstract: A programmable device architecture that may improve functionality over look-up table based or product-term based programmable logic devices and that may provide for the efficient implementation of user-programmable logic designs resulting in implementations that may require less area and may provide increased performance. A product-term array (either fully or partially populated) may be placed in front of a number of LUT-based macrocells, utilizing the available routing wires as wordlines to form the product terms. The present invention takes advantage of existing routing to do more than just route signals from one point to another by allowing logic to be implemented in the same die area. The result is logic implementations that may require fewer total macrocells, fewer levels of macrocells, and fewer point-to-point nets (because logic density increases). The present invention may apply to FPGAs comprising an array of macrocells and to FPGAs comprising an array of clustered macrocells.

Abstract: A circuit and method used in LC or ring oscillators. The present invention may modulate the frequency of oscillation by detecting a quadrature signal and controlling the sign and magnitude of the quadrature signal that may be feedback to the oscillator to cause the oscillator to run either faster or slower (dependent on the sign of the quadrature signal) than the unmodulated oscillator.

Abstract: A product-term array that may allow for the implementation of product terms requiring less silicon area than conventional designs. The product terms may also have a shorter propagation delay when compared with conventional designs. A multiplexer, which may be programmed with a configuration bit or signal, may select the polarity of an input signal to the product-term array. Duplicating a number of the initial inputs to the array may accommodate particular design constraints that may require both polarities (i.e., both positive and negative) of a given signal or set of signals. Even with the duplication of certain inputs, the total number of product-term inputs to the array will generally be reduced when compared with conventional designs, that duplicate the polarity of every input internally to the array.