Abstract: An architecture comprising a detector, a first pump circuit, a second pump circuit and a comparator. The detector may present a first active operating signal in response to one or more reference signals. In one example, the first active operating signal may be generated in response to a feedback signal having a parameter within a predetermined range. The first pump circuit may be configured to provide a replica pump signal in response to a current adjustment signal and either (i) at least one of the one or more reference signals or (ii) the first active operating signal. The second pump circuit may be configured to provide a voltage control signal in response to the current adjustment signal and either (i) the first active operating signal or (ii) a second, independent active operating signal. The comparator may be configured to provide the current adjustment signal in response to the replica pump signal and the voltage control signal.

Abstract: The invention enables a die to be attached to a die attach pad so as to reduce delamination stress that can arise when the die and die attach pad are heated, and so as to provide support for the die at locations where bond pads are formed so that the die is not damaged by forces applied to the die during attachment of bond wires to the bond pads. The die and die attach pad so attached can be used to produce a packaged die having improved delamination characteristics, so that the cost to manufacture and/or store the packaged die can be reduced. The invention further provides die attach pads and leadframes including such die attach pads that are particularly suited to achieving the aforementioned functional characteristics.

Abstract: The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) an internal select signal and (ii) a control signal in response to one or more chip select signals. The second circuit may be configured to generate a sleep signal in response to (i) said control signal and (ii) a clock signal.

Abstract: A programmable skew buffer for optimizing the timing at the input or output pins of a memory device. The timing at each input and output pin of the memory device can be adjusted on an independent basis by coupling each input or output pin to a separate programmable skew buffer. The programmable skew buffer includes a clocked storage element that receives data from an input pin and outputs data to the memory array in the memory device when optimizing the input timing of the memory device, or receives data from the memory array in the memory device and outputs data to an output pin when optimizing the output timing of the memory device. The programmable skew buffer also includes a programmable delay circuit which generates one of a plurality of clock signals wherein each signal represents a delayed version of the system clock.

Abstract: A high voltage switch for use in an EEPROM/FLASH memory that may be implemented using a twin-well process (e.g., using only P-channel transistors). The circuit comprises a positive switch configured to present a first and a second switch signal in response to (i) one or more select signals and (ii) an address signal and a second switch configured to present a programing voltage in response to (i) the select signals, (ii) the first and second switch signals and (iii) a high voltage source. A high voltage positive and negative pump may provide the high voltage source.

Abstract: A circuit comprising a first and second bitline, a plurality of groups of memory cells and a control circuit. The first and second bitlines may each be configured to read and write to one or more of the plurality of groups of memory cells. Each of the plurality of bitline pairs may be interdigitated. The control circuit may be configured to select an active group of said plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.

Abstract: A NAND stack array (95') is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

Abstract: A structure and process for a gouge-free substrate non-volatile memory cell with a floating gate, field effect transistor and a select gate transistor. The cell includes a floating gate, field effect transistor and a select gate transistor wherein the select gate transistor comprises a first conductive layer covered by a second conductive layer wherein electrical contact is made to the first conductive layer. The invention contemplates that the first and second conductive layers can be separated by an insulative layer. The invention also contemplates that the first and second conductive layers may be of different cross-sectional areas, wherein the cross-sectional area of the first conductive layer is larger than the cross-sectional area of the second conductive layer and wherein electrical contact is made to the first conductive layer at a sight not encompassed or covered by the second conductive layer.

Abstract: A tube protector device includes a first cap member, the first cap member being configured to fit over and substantially seal a first end of a tube; a second cap member, the second cap member being configured to fit over and substantially seal a second end of the tube; and a fastening device adapted to resiliently bias the first cap member toward the second cap member. At least the first cap member includes a collar configured to surround a portion of an outer surface of the tube and an angled tube support member configured to fit within the internal diameter of the tube, the collar and the angled support being configured to receive the first end of the tube therebetween. The first cap member further includes a sealing member, a particle barrier and/or a shock absorber between the collar and the angled support member.

Abstract: An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. The insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment.

Abstract: A circuit comprising a first voltage shifter, a second voltage shifter and a comparator configured to control a switchable current source. The first voltage shifter may be configured to provide a first reference voltage signal in response to a reference input signal. The second voltage shifter may be configured to provide a second reference voltage signal in response to the reference input signal. The comparator may be configured to control a switchable current source in response to said first and second reference voltage signals.

Abstract: A wetting layer is formed on a substrate at a relatively high process temperature (e.g., the temperature of the substrate and/or the temperature within a process chamber in which the wetting layer is formed). A metallization layer that is subsequently formed on the wetting layer adheres to the wetting layer better than the metallization layer would adhere to the wetting layer if the wetting layer was formed at a lower process temperature. The high process temperature causes the density of the wetting layer to be increased, so that, consequently, the wetting layer has a smoother surface to which the metallization layer can adhere.

Abstract: A reduced complexity, dynamic pull-up suppressor for column redundancy write schemes with redundant data write lines is provided. Logic values of input data signals during the width of an internal write pulse are used to reduce the redundant data line crowbar while at the same time increasing the speed of the write to a redundant column. The full recovery capability of dynamic pull-up circuits, which are all enabled to speed up the recovery of the redundant data write lines at the end of the write operation, is available. The data write bus is separated from the redundant write lines, thus ensuring a consistent loading of the data write bus independent of whether redundancy is used or not. According to one embodiment, a circuit including dynamic pull-up elements configured to drive a redundant data line of a memory device to a logic state according to a state of an input data signal is provided.

Abstract: A method, circuit and apparatus is provided for preserving and/or correcting product engineering information. Non-volatile storage devices reserved for receiving product engineering bits can either be contained in at least three separate storage locations spaced from each other across the integrated circuit or, alternatively, be contained in a single storage location area with error correction bits and/or words added to that location. In the first instance, redundant product engineering bits are written to each storage location. Product engineering bits read from a majority of those locations which have identical values are deemed valid. The addition of extra bits and/or words can be combined with the possibly defective product engineering bits to correct errors in those bits.

Abstract: One or more optimized programming or erase parameters is (are) determined for a programmable device and that parameter (or those parameters) is (are) stored in the programmable device. When the programmable device is to be programmed or erased, the optimized parameter (or parameters) is (are) read from the programmable device and used in the programming or erase process.

Abstract: A nonvolatile memory circuit that includes a load circuit coupled to a band-gap reference circuit and a nonvolatile memory cell. The load line circuit is configured to provide a programming voltage to the nonvolatile memory cell. The programming voltage may be generated in response to the reference voltage generated by the band-gap reference circuit. The nonvolatile memory circuit may also include an amplifying circuit that amplifies the reference voltage of the band-gap circuit, and provides the amplified reference voltage to the load circuit. The nonvolatile memory circuit may further include a voltage trim circuit that trims the amplified reference voltage and provides the trimmed amplified reference voltage to the load circuit. The reference voltage, amplified reference voltage, and the trimmed amplified reference voltage may each output a stable voltage that is independent of variations in process parameters, operating temperatures, and supply voltages of the nonvolatile memory circuit.

Abstract: An integrated circuit, apparatus and method is provided for programming manufacturing information and software program information upon non-volatile storage elements on the integrated circuit. The manufacturing information includes information as to a specific processing recipe or layout used to form hardware of the integrated circuit. The software information indicates a specific revision of software used to program the integrated circuit, or a programming tool used to input the software into the integrated circuit. Combination of software and hardware is therefore embodied in non-volatile storage elements as product engineering bits. The product engineering bits can be called upon and read by the manufacturer or by the customer outside normal operation of the integrated circuit. A comparison of the hardware and software revisions will indicate possible incompatibility.

Abstract: The present invention advantageously provides a method and apparatus for polishing a semiconductor topography by applying a liquid which is void of particles between the topography and an abrasive polishing pad surface. The semiconductor topography is rotated relative to the polishing surface to polish elevationally raised regions of the topography. The particles are fixed within the polishing surface which may comprise a polymeric material. In one embodiment, the liquid may comprise water diluted with acid. If the liquid is adjusted to have a pH between 6.0 and 7.0, the polishing process may be used to remove a silicon dioxide layer from the topography at a faster rate than a silicon nitride layer residing beneath the oxide layer. Alternately, a metal may be selectively removed from above an oxide layer if the polishing liquid has a pH between 2.0 and 5.0. In another embodiment, the liquid may be deionized water. The water does not react with the material being polished.

Abstract: A two-transistor, zero DC power, non-volatile inverter latch that can be made using floating-gate or SONOS technology to provide a consistent and/or reliable logic high and/or logic low output level. The inventive cell is useful for holding option settings in any custom integrated circuit or, more specifically, for holding configuration information (e.g., ASIC, PLD or FPGA interconnect data; configuration data for such ICs or for a clock/oscillator circuit or a microcontroller, etc.). The inventive cell outputs the data state immediately on power-up without any need for recall sequencing. The benefit of the invention comes from the potential for a very small cell which, in many applications, can substitute for non-volatile RAM.