Abstract: A circuit configured to generate an error signal that may be used to disable a loading mechanism (such as a loading mechanism in a wafer sorter). The circuit comprises a wafer sense circuit configured to generate a first pulse in response to a wafer passing a detection point, a pulse generator circuit configured to generate (i) a second pulse in response to a transition (e.g., a positive transition) of the first pulse and (ii) a third pulse in response to a transition (e.g., a negative transition) of the first pulse. An error detection block may be configured to generate an error signal in response to (i) the first pulse, (ii) the second pulse and (iii) the third pulse.

Abstract: A cache memory system connected between an input/output system having an input/output processor and a computer system having a system bus and a main memory with an input/output portion is provided in which data requested by the input/output processor is retrieved from the input/output portion of the main memory, a memory stores the requested data, and the data in the memory is updated either when the processor is not requesting data or when the processor is requesting data already in the memory. A method for replacing memory pages within a cache memory system is also provided.

Abstract: An output buffer is provided in which the output impedance of the buffer is set relatively low during an initial portion of an output transition. Subsequently, near the end of the output transition, the output impedance of the buffer is increased to more closely follow the characteristic impedance of a transmission line driven by the buffer. The output impedance is automatically changed when the buffer output voltage crosses a predetermined threshold. The output buffer includes a voltage threshold detection circuit comprising a diode and a transistor, the diode being coupled to the gate of the transistor. When a voltage level of a signal applied to one of the diode and the transistor crosses a predetermined threshold, a switch state of the diode and/or transistor changes to thereby change an output of the voltage detection circuit and trigger the change of output impedance of the output buffer in a reliable and consistent manner.

Abstract: A method and apparatus for generating a serial test pattern for sequence detection. The serial test pattern has a first plurality of bits and is generated by a pattern generator. A second plurality of bits is generated having a first value. The second plurality of bits includes less bits than the first plurality of bits. The first value of the second plurality of bits is then compared with one or more numbers to generate a comparison result. A next bit is then generated in the serial pattern based upon the comparison result and one or more bits of the second plurality of bits.

Abstract: An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. T he insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment.

Abstract: A circuit comprising a main memory array with a block of columns per data I/O, a main read/write block per block of columns, one or more spare memory columns, a bad address detector circuit per spare column, and a read/write block per spare column. A spare column may replace a defective column or cell in any of the blocks of columns. The spare column may be read from/written to via the main read/write block of the column it is replacing, or via its own dedicated read/write block to improve access times. The bad address detector can be configured with programmable elements to produce a control signal when the address of a defective memory element (cell or column) is applied. This signal is then used to disable the defective memory element (and read/write block) and enable a spare column (and read/write block) in its place. The present invention also comprises a recovery circuit on the local data lines (multiplexed to the addressed bitlines).

Abstract: A driver circuit is presented for producing particular output voltage levels at high speeds using a current switching technique. The circuit employs driver transistors connected in series between switchable current sources. The driver transistors switch current within the current sources through a resistor coupled between an output of the driver circuit and a reference terminal voltage. Switching the current occurs in rapid fashion within an opened loop arrangement. The switchable current sources are configured so that current is present through the current sources whenever a corresponding driver transistor is turned on. Current through the current sources, as switched through the resistor separating the reference terminal voltage and the driver output, is regulated by a closed loop replica circuit. The replica circuit may include an opamp whose output operably produces the regulated current via feedback from the current path to an input of the opamp.

Abstract: A sense amplifier that includes a sensing circuit, a first feedback circuit, and an output buffer. The first feedback circuit is coupled to an output of the sensing circuit and is configured in a feedback arrangement with the output buffer. The output of the sensing circuit provides an output signal having a first slew rate as the output signal transitions from a first logic state to a second logic state. The first feedback circuit may increase the slew rate of the output signal. The sense amplifier may also include a second feedback circuit coupled to the output of the sensing circuit and configured in a feedback arrangement with the output buffer. The second feedback circuit may increase a second slew rate of the output signal as the output signal transitions from the second logic state to the first logic state. The sense amplifier may be a current sense amplifier that may be used to sense the amount of current flowing through a nonvolatile memory circuit.

Abstract: A circuit that may be used as a memory cell that may be capable of a differential write and a single ended read. The circuit generally comprises a memory storage element having a write bitline, a complement write bitline and a read bitline. One or more first gates may be configured to pass data on the write bitline and the inverted write bitline during a write operation. The write operation may occur in response to a write control signal. A second gate may be configured to pass data on from the storage element to the read bitline in response to read control signal. As a result, the circuit may be written by both the write bitline and the complement write bitline and may be read by the read bitline.

Abstract: The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.

Abstract: A system for determining one or more critical dimension(s) of a semiconductor structure comprising a scanning electron microscope and a parallel distributed process operationally connected to an output of a scanning electron microscope. Said parallel distributed process containing coefficients that provide a multi dimensional mapping space for the output of said scanning electron microscope to map to an output value that provides information on the dimensions of the semiconductor structure.

Abstract: An improved clock generation circuit is provided for changing the phase of one signal relative to the phase of another signal. Both signals presented to the clock generation circuit transition at the same frequency. One or both of those signals are delayed by dissimilar amounts to skew the phase difference between the signal pairs and 90.degree.. A phase detector, or logic gate, determines a phase differential between the incoming signals. A charge pump and storage device maintain a voltage level commensurate with that difference. The stored voltage is then used to control a feedback loop coupled from the output of the detector to a current path which traverses a buffer coupled between an input signal and a phase compensated output signal. The current path receives current necessary to change both the rise and fall rates produced by the buffer. According to another embodiment, two feedback loops may be used for a corresponding pair of buffers.

Abstract: An apparatus and method for testing a communication device using a loopback path. A circuit is used to internally generate a test packet and to check the test packet once the test packet is transmitted through a loopback path within the communication device. The loopback path includes a data path from a test transceiver, through a first path within the core logic, at least one selected physical transceiver, a second path within the core logic and back to the test transceiver.

Abstract: An integrated circuit, apparatus, and a method is provided for programming and reading manufacturing information upon non-volatile storage elements of the integrated circuit. The manufacturing information includes the particular processing recipe and layout of the integrated circuit, each recipe or layout indicative of a specific hardware revision. The storage elements may be programmed prior to assembling the integrated circuit within a semiconductor package, and the programmed elements are read prior to shipping the packaged integrated circuit to a customer. If the read hardware revision is not qualified for release, the product will be placed in a staging area and prevented from shipping to a customer or end user. Thus, the programmed hardware revision serves to gate product at test before shipping that product to a customer.

Abstract: The invention relates to a voltage reference source used to control an overvoltage tolerant input/output buffer for a mixed voltage bus system. The voltage source comprises a voltage tracking circuit having a first input receiving a variable voltage, and a second input receiving a reference voltage, the voltage tracking circuit being adapted to generate an output voltage in response to the difference between the variable voltage and the reference voltage, wherein where the variable voltage is less than the reference voltage, the output voltage is held at substantially zero volts. When the variable voltage exceeds the reference voltage, the output tracks the voltage at the variable voltage input.

Abstract: The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input buffers of both the address path and the clock path include input buffer cells configured to reduce timing delay differences caused by process variations while minimizing current leakage. An exemplary input buffer cell described herein includes a first inverter stage with a pair of NMOS devices connected in series with a PMOS device and a second inverter stage having an additional PMOS device connected along a feedback path around an inverter. The PMOS device along the feedback path operates to assist the pair of NMOS devices to pull a voltage input to the inverter to a high logic state, when an input to the cell is held low, to prevent leakage current through the inverter.

Abstract: A memory array having a physical depth of 2N-bits (N being an integer) includes control and data bus logic configured to control read and/or write operation in the memory array and to select the depth of the memory array. The control logic may include upper and lower byte control circuitry and the depth of the array may be selected from a group consisting of xN-bits and 2xN-bits, x being an integer. The control and data bus logic may be implemented as metal options within the device to be selected during fabrication to achieve a desired array depth.

Abstract: A fluid delivery system is provided having a degas module which can be retrofitted to allow early detection of degas defects within the system. A degas chamber is modifiable to include at least one view port into which an operator can visually examine leaks within a fluid-carrying tube existing exclusively within the degas chamber. Liquid leaking from the tube, or particles possibly entering the tube, can be readily detected through the view port prior to harming any downstream processing operations. In addition to the view port, a purge port can be provided through which a purge gas is transmitted during times when potential backstreaming can occur. The purge gas alleviates unwanted gases from interacting with the volatile leaking liquid. This helps minimize particulate formation in or around the leak and, specifically, particulates entrained within the liquid forwarded to the downstream processing tool.

Abstract: A method of forming a field oxide or an isolation region in a semiconductor die. An oxidation mask layer (over an oxide layer disposed over the substrate) is patterned and subsequently etched, preferably so that the oxidation mask layer may have a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the sidewall of the oxidation mask layer. A field oxide is then grown in the recess using a dry oxidizing atmosphere. The sloped sidewall of the substrate recess effectively moves the face of the exposed substrate away from the edge of the oxidation mask layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and less field oxide thinning. The preferred range of slopes for the substrate sidewall is from approximately 10.degree. to 40.degree.

Abstract: An output buffer includes a differential data circuit for generating a first and a second differential signal, a pulse circuit for generating a pulse signal, a first latch circuit set by the first differential signal and reset by either the pulse signal or the second differential signal and a second latch circuit set by the second differential signal and reset by either the pulse signal or the first differential signal. An output circuit generates an output signal, the output signal being tri-stated whenever the pulse signal resets the first and second latch circuits. A method for improving output tri-state time of an output buffer includes the steps of pre-charging first and the second differential data inputs; tri-stating the buffer output upon each assertion of a timing signal; switching the output out of tri-state and into either a first or a second logic state only when one of the first and second differential data inputs changes to an active state; and returning to the pre-charging step.