Abstract: A method and apparatus comprising a first circuit configured to generate a first output in response to a first input, a second circuit configured to present a second output in response to a second input, and a third circuit configured to generate a first voltage signal and a second voltage signal in response to the first output and said second output. The first voltage signal may be above the positive supply and the second voltage signal may be below the negative supply.

Abstract: A USB-to-USB connecting device is provided for interconnecting two independent universal serial buses (USBs) and for synchronizing local device clocks to the data streams of both USBs. To interconnect the USBs, the device may include a separate local clock synchronization mechanism for each USB connected to the device. Each separate local clock synchronization may utilize the same reference clock. A method for interconnecting two USBs is also provided.

Abstract: A trench-isolated active device and a method of forming a trench-isolated active device on a semiconductor substrate wherein the conductive layer of the device is self-aligned with an isolation trench is disclosed. The method includes applying a conductive layer over a dielectric layer (e.g., gate oxide), forming an opening in the conductive layer and the dielectric layer, forming a trench in the substrate corresponding to the opening, passivating the side walls of the trench with a dielectric material, and filling the trench with a dielectric material. The structure includes a semiconductor substrate having a trench defining a cell region, conductive material in the cell region and adjacent to the trench, and a layer of dielectric material on the side walls of the trench and on the conductive material adjacent to the trench. The invention further contemplates that the trench contains dielectric material, preferably soft glass.

Abstract: A buffer comprising a plurality of storage elements, a write pointer configured to indicate a particular storage element to write data received from an input data stream and a plurality of read pointers, each configured to indicate a particular data location to read data from to generate a number of output data streams. The input data stream and the output data streams may be part of a data communications device.

Abstract: A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read data signal. The present invention generally comprises a three-level receiver, a latch and an output driver to form a one-pin bidirectional interface used with a shift register. To write, the interface converts a three-level input signal into separate clock and data signals which drive the shift register. To read, the interface converts a bi-level input signal into a three-level output signal representing the output of the shift register. As a result, the present invention allows the programming of a device such as an erasable programmable read only memory (EPROM) in a clock chip while utilizing the fewest number of pins.

Abstract: A circuit and method for generating an evaluation signal used to turn OFF one or more sense amplifiers. The sense amplifiers may be configured to present a first and second output in response to (i) an input signal and (ii) an enable signal. A detect circuit may be configured to present a detect signal in response to the first and second outputs. A control circuit may be configured to present the enable signal in response to (i) the detect signal and (ii) a wordline signal.

Abstract: A circuit and method for controlling a wordline and/or stabilizing a memory cell comprising a first circuit and a second circuit. The first circuit may be configured to generate a control signal in response to (i) a select signal and (ii) an equalization signal. The second may be configured to generate an output signal in response to (i) the control signal and (ii) a global wordline signal. The output signal may be presented to one or more memory cells of a memory array.

Abstract: A detector circuit may detect a peak value of at least one input voltage and may provide the peak value as an output for use by other circuitry capable of being coupled to the detector circuit. Pairs of differential inputs may be employed, using n-channel transistors (in one example), and using diodes to capture the peak at a shared output node. Each differential pair has two constant current devices connecting the source/drain paths to the terminal of a voltage supply. This circuit enables the use of high input voltages which may be at or near the upper power supply (e.g., V.sub.DD). The circuit is in effect a negative peak detector, capturing the most negative value of at least one input level and holding that level, with a slow leakage of the held value back toward the upper voltage supply with a time constant that is generally set much slower than the input signal transition frequency. A similar circuit may be implemented using p-channel transistors in the differential pairs, to detect positive peaks.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuitry for synchronizing the asynchronous logic derived clock signal to be a reference clock signal is coupled to the circuitry for generating. The circuitry for synchronizing generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal but only when the input signals are recognized as clocking signals. That is, the synchronizing circuitry discriminates between valid input signals and spurious signals or noise. Further, the programmable device includes circuitry for suspending a clock signal. In one embodiment, input signal having at least a minimum duration is received and used to generate an asynchronous logic derived clock signal.

Abstract: An apparatus comprising a phase-locked loop, a select circuit and a control circuit. The phase-locked loop may be configured to generate a feedback signal (along with a buffered output signal) in response to a reference clock and a control signal. A select circuit may be configured to present a reference clock signal in response to a plurality of input clock signals and a select signal. The slew control circuit may be configured to generate the control signal in response to the select signal, and the feedback signal. The control circuit may be used to reduce noise presented to the phase-locked loop and may allow for a rapid initial frequency acquisition of the PLL to the reference frequency.

Abstract: A memory device includes a low complexity, easy delay tuning, balanced-delay "combine control signals" (CCS) block, driven by slow slope control signals directly from the first stage (preferably not later than a weak inverter used in the hysteresis feedback portion) of a stabilized trip point input buffer. The CCS block is able to generate global internal write pulses appropriately timed with respect to circuits gating a data write to bitline access with an address transition detection (ATD) pulse, in order to provide stable, improved and balanced (between a plurality of control signals which can individually initiate and/or end a write in multiple distinct combinations) write parameter margins for the memory device. A three-step delay adjustment method for the CCS block and related data delay blocks is also provided.

Abstract: An interruptible state machine includes a state machine and an interrupt processor. The interrupt processor minimizes the required total number of states for the state machine when it must return to its next "normal" state after an input or interrupt that may occur at any of its normal states. In response to the interrupt, the interrupt processor stores the next state, processes the interrupt, and restores the next state after precessing the interrupt.

Abstract: A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.

Abstract: A phase detector circuit comprising a pump-up circuit and a pump-down circuit. The pump-up circuit may be configured to generate a pump-up signal in response to (i) a data signal, (ii) a half-rate clock signal and (iii) a quadrature of the half-rate clock signal. The pump-down circuit may be configured to generate a pump-down signal in response to (i) the pump-up signal and (ii) the quadrature of the half-rate clock signal.

Abstract: A circuit comprising an oscillator, a multiplexer, a half rate clock circuit and a full rate clock circuit. The oscillator may be configured to generate a first clock signal and a second clock signal in response to a control signal. The multiplexer may be configured to generate the control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal. The half rate clock circuit may be configured to generate the half rate clock signal in response to the first and second clock signals. The full rate clock circuit may be configured to generate the full rate clock in response to (i) one of the first and second clock signals and (ii) a reference clock.

Abstract: A circuit comprising a pump-up circuit and a pump-down circuit. The pump-up circuit may be configured to generate a pump-up signal in response to (i) a data signal and a clock signal. The pump-down circuit may be configured to generate a pump-down signal in response to (i) the data signal, (ii) the clock signal, and (iii) a quadrature of the clock signal. The pump-down circuit and the pump-up circuit are generally independent circuits.

Abstract: A method and apparatus for determining and recovering from a USB micro-controller busy condition, wherein a toggle variable indicative of whether the USB micro-controller is in the busy condition or not is stored in a memory, and a counter is incremented if the toggle variable is set. The counter is checked to determine if the counter has reached a predetermined count, and if so data lines of the USB micro-controller are disconnected from a USB bus coupled to the USB micro-controller for a predetermined amount of time to cause a USB host computer coupled to the USB micro-controller to re-initialize the USB micro-controller. The memory contains a data structure including fields for storing the toggle variable, and a count indicative of how many times the toggle variable has been set for implementing the counter.

Abstract: A non-volatile memory cell includes a floating gate having a bottom surface in contact with a tunnel layer formed on the substrate, a top surface, and sidewall surfaces oriented along the bitline direction and along the wordline direction of the memory cell. A dielectric layer covers at least a portion of the top surface and covers at least a portion of the surfaces oriented along the bitline and wordline directions. A control gate overlaps the floating gate over substantially all of its surface area. A plurality of self-aligned sidewall spacers are provided, disposed against at least the dielectric layer and the control gate sidewalls. By overlapping the control gate over the floating gate, a greater surface area is made available for charge storage and/or for increasing the coupling ratio of the memory cell. This allows the width of wing structures to be decreased, while maintaining a high coupling ratio.

Abstract: An efficient design to generate a programmable almost empty or programmable almost full flags. The present invention accomplishes this by efficiently evaluating the read count minus write count plus a user programmed offset being greater than or equal to zero for the programmable almost empty flag generation. Similarly, evaluating write count minus the read count plus the user programmed offset minus the size of the FIFO is greater than or equal to zero for the programmable almost full flag generation. The counters in the FIFO count from 0 to twice the size of the FIFO minus one and the user programmed offset can be between 0 to the size of the FIFO minus one. The offset has one less bit than the read and write counters. The processing block masks out the higher order bits of the Offset input based on the size of the FIFO. The first stage performs the bit wise addition of the offset, read counter and write counter inputs without any carry chain propagation.

Abstract: A circuit including an address bus providing random addresses for a random access memory array, and a register configured to receive, store or transfer (i) a first random address from the address bus in response to a first periodic signal transition and (ii) a second random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle, and are preferably complementary to each other.