Abstract: An output buffer includes a differential data circuit for generating a first and a second differential signal, a pulse circuit for generating a pulse signal, a first latch circuit set by the first differential signal and reset by either the pulse signal or the second differential signal and a second latch circuit set by the second differential signal and reset by either the pulse signal or the first differential signal. An output circuit generates an output signal, the output signal being tri-stated whenever the pulse signal resets the first and second latch circuits. A method for improving output tri-state time of an output buffer includes the steps of pre-charging first and the second differential data inputs; tri-stating the buffer output upon each assertion of a timing signal; switching the output out of tri-state and into either a first or a second logic state only when one of the first and second differential data inputs changes to an active state; and returning to the pre-charging step.

Abstract: An Asynchronous Transfer Mode ATM receiver is disclosed. The ATM receiver comprises an input that receives an ATM cell. A first-in first-out (FIFO) is coupled to the input. The FIFO stores the ATM cell received from the input. A header error correction (HEC) checking circuit is coupled to the input. The HEC checking circuit starts to check a header in the ATM cell for an error at substantially the same time when the ATM cell is being stored in the FIFO.

Abstract: A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five "window" intervals. The "window" intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth.

Abstract: An input buffer is provided which can function as either a voltage referenced input buffer or a non-voltage referenced input buffer. The input buffer includes a circuit which is selectively configurable in one of the two different modes of operation in response to a mode signal, wherein in a first mode of operation a reference signal is operative to constrain a trip point of the input buffer. A single circuit with a capability of fulfilling both roles allows the decision as to which mode of input buffer is to be used to be deferred until it has been determined which mode is most suitable for a particular application.

Abstract: The present invention provides a design method and apparatus for improving the testing of devices having status flags that indicate when particular boundary conditions are met. The present invention enables a subset of the overall device architecture that requires much less testing and vector analysis to fully analyze the device characteristics. The smaller subset of the device maximizes the number of in-depth analysis tests that can be run to provide a reliable tested device. After the tests are run on the smaller subset of the device, a smaller subset of tests may be executed on the entire full depth array with confidence that the in-depth tests have been previously executed. The present invention method and apparatus can be enabled during design, device characterization and production test phases of the product.

Abstract: A circuit and method for staggering a bitline precharge between particular sections of a memory array. The present invention may be implemented in memories having increasing depths to reduce unacceptably high precharge current requirements associated with high bitline loads. Since the particular memory sections of the memory array are turned on independently, the peak current necessary to charge the particular bitlines is limited. The present invention may be implemented in logic and may therefore be less sensitive to process and temperature variations.

Abstract: An integrated circuit, a programming mechanism and a method are provided for programming manufacturing information upon non-volatile storage devices of the integrated circuit. The storage devices may be programmed after manufacture and prior to assembling the integrated circuit within a semiconductor package. Thereafter, the packaged circuit can be tested to determine where, how and when the integrated circuit was manufactured from among possibly numerous die within a wafer and wafer lot. The storage locations which receive manufacturing indicia are addressed in an address location entirely separate from the addresses which receive data during normal operation of the integrated circuit. Accordingly, manufacturing information is accessible by the manufacturer, and the customer is preferably made unaware of the address space employing those storage locations.

Abstract: The hardware semaphore generates an interrupt signal upon a change in ownership status of a shared resource. In particular, the semaphore apparatus generates an interrupt signal when a requesting device or process relinquishes control of a shared resource. By generating a hardware interrupt when a shared resource becomes available, devices or processes that require access to the resource need not repeatedly poll the hardware semaphore to determine if the resource associated with the semaphore is available. In a preferred embodiment, the hardware semaphore apparatus employs a pair of cross-coupled NOR gates for arbitrating between two requesting devices. A pair of rising edge detectors and flip-flops are connected to outputs of the NOR gates for generating the interrupt signal. Other exemplary and illustrative embodiments are described as well.

Abstract: A state machine for generating a flag that represents the fullness of a FIFO buffer is disclosed. The present invention generates a set of next state variables that are derived generally from a combination of three previous state variables and three additional inputs representing an internally generated look-ahead flag, an external write clock and an external read clock. The next state variables are derived specifically from a product of the previous state variables and complement signals of the previous state variables. The full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal and a look-ahead decoded internal full flag signal. An empty flag can be generated by switching the read and write clock inputs and changing the look-ahead decoded internal full flag to a look-ahead decoded internal empty flag.

Abstract: The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.

Abstract: The invention enables the identification of particles in a chamber in which a substrate is processed (e.g., a semiconductor process chamber). Such identification can be accomplished by placing a test substrate [(i.e., a substrate that is examined to detect and identify particles present on the substrate)] in the process chamber and inspecting the test substrate, where the composition of the test substrate is chosen so as to enable identification of particles having a composition that includes one or more of a predefined set of elements. For example, the composition of the test substrate can be chosen so that each of the elements that substantially comprise the composition of the test substrate are different than each of the elements that substantially comprise the composition or compositions of a process substrate or substrates [(i.e.

Abstract: A reference voltage generator may include an input for receiving a first voltage for input to a sense amp. The reference voltage generator may also include an output for outputting a second voltage for input to the sense amp. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first bitline. The reference voltage generator may also include a first output for outputting a second voltage on a second bitline. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first transmission busline. The voltage generator may also include a first output for outputting a second voltage on a second transmission busline. The second voltage is influenced by the first voltage.

Abstract: A system and method for reconfiguring a peripheral device connected by a computer bus and port to a host from a first generic configuration to a second manufacturer specific configuration is provided in which the configuration of a peripheral device may be electronically reset. A peripheral interface device for a standardized computer peripheral device bus and port is also provided in which a physical disconnection and reconnection of the peripheral device is emulated to reconfigure the bus and port for a particular peripheral device.

Abstract: An apparatus for protecting an integrated circuit against damage from electrostatic discharges (ESD) includes a single ESD bus that is connected to multiple input pads through a respective diode. The ESD bus is isolated from the positive power supply bus V.sub.DD. The ESD bus is coupled to the negative power supply bus V.sub.SS by a FET-triggered SCR circuit. ESD charge on an input pad forward biases the respective diode and charges the ESD bus. When the voltage of the ESD bus reaches a predetermined threshold voltage, the FET breaks down, and triggers the SCR circuit to shunt the charge on the ESD bus to V.sub.SS. The threshold voltage is selected such that, in normal operation, voltages higher than V.sub.DD may be applied to the input pad without input leakage current.

Abstract: A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

Abstract: A circuit for presenting one or more current source outputs which may be used to optimize the interface between optical components in a computer system. The multiple currents may be independently varied in each particular component to provide a current adjustment for proper functioning of a wide variety of LEDs and photo transistors. As a result, a dynamic optimization of the devices is provided. Since the present invention allows a wide variety of optical components to be used, the overall cost of implementing the device may be reduced.

Abstract: An integrated circuit including a first input for receiving a scan enable control signal and a second input for receiving a test mode control signal. The integrated circuit also includes a programmable scan circuit coupled to the first input and the second input. The programmable scan circuit configures the integrated device to operate in a default mode, a scan mode, or a test mode in response to the scan enable and test mode control signals.

Abstract: The present invention describes a method for forming an interconnect to a region of an electronic device. The method comprises the steps of: forming a conductive material layer, wherein the conductive material layer fills an opening in a first dielectric layer and is disposed over the first dielectric layer; applying a patterning layer over the conductive material layer, wherein the patterning layer exposes a portion of the conductive material layer; etching the conductive material layer to remove the portion of the conductive material layer in order to provide an exposed conductive material structure that protrudes above the dielectric layer; forming a second dielectric layer; and planarizing the second dielectric layer to expose a portion of the exposed conductive material structure.

Abstract: A robust system for entering a test mode in an integrated circuit, for example, a memory device, greatly eliminates the probability of unintentionally entering the test mode, yet provides a system of access through a precise address and control pin sequence. By using an existing control pin present on the integrated circuit as a clock signal input for a series of latches, the present scheme sets up a number of address with predetermined values in order to create a key that is correct only if all the addresses are at the correct values. The key, combined with the clock signal input, allows a test mode enable signal to pass through each latch in a series. By further requiring that the address sequence for the key be input during an otherwise "illegal" operation for the integrated circuit, the present scheme further ensures that unintentional entry to the test mode is avoided.

Abstract: A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors that are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.