Abstract: A semiconductor device includes a semiconductor substrate; and a through electrode that penetrates the semiconductor substrate. The semiconductor substrate has a groove structure that is positioned between a peripheral edge of the semiconductor substrate and the through electrode.

Abstract: A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.

Abstract: A system includes a first device, a second device, and a bus interconnecting the first and second devices to each other, wherein the first device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a first data electrode, and a first data control circuit coupled to the first control logic circuit and the first data electrode.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command.

Abstract: A semiconductor device is provided with a clock output control circuit which supplies a long-period clock signal having a period longer than an internal clock signal within an active period and supplies the internal clock signal within a read period subsequent to the active period, a clock transfer circuit which transfers the internal clock signal and the long-period clock signal outputted from the clock output control circuit, a data input/output terminal, and an input/output circuit which outputs read data to the data input/output terminal in synchronization with the internal clock signal having been transferred by the clock transfer circuit.

Abstract: A semiconductor device is provided with a control circuit generating a plurality of first control signals indicating timings at which column switches conduct at the time of reading and a plurality of second control signals indicating timings at which the column switches conduct at the time of writing. The control circuit activates the plurality of first control signals such that timing at which the data read from each of memory cell arrays arrives at a FIFO circuit after reception of a read instruction from outside is the same in each bank and activates the plurality of second control signals such that the column switches match a timing at which write data input from outside to a first data input/output terminal arrives at the corresponding column switch.

Abstract: A crystal material lattice strain evaluation method includes illuminating a sample having a crystal structure with an electron beam in a zone axis direction, and selectively detecting a certain diffracted wave diffracted in a certain direction among a plurality of diffracted waves diffracted by the sample. The method further includes repeating the illuminating step and the selectively detecting step while scanning the sample, and obtaining a strain distribution image in a direction corresponding to the certain diffracted wave from diffraction intensity at each point of the sample.

Abstract: A system includes a control chip and a plurality of command terminals receiving a plurality of command signals, respectively; a command decoder coupled to the command terminals, the command decoder being configured to output an internal command in response to the command signals; and a layer address buffer configured to output a layer address each time the command decoder outputs a row command as the internal command and outputs a column command as the internal command; and a plurality of core chips stacked with one another, each of the core chips being configured to receive the, row command and the layer address output together with the row command, to receive the column command and the layer address output together with the column command, and to free from receiving the command signals.

Abstract: A device includes a semiconductor substrate, a first penetration electrode and a plurality of second penetration electrodes each penetrating the semiconductor substrate, a first terminal and a plurality of second terminals formed on a one side of the substrate, and a third terminal and a plurality of fourth terminals formed on an opposite side of the substrate. Each of the first and third terminals is vertically aligned with and electrically connected to first penetration electrode. Each of the second terminals is vertically aligned with an associated one of the second penetration electrodes and electrically connected to another one of the second penetration terminals that is not vertically aligned with the associated second terminal. Each of fourth terminals is vertically aligned with and electrically connected to an associated one of the second penetration electrodes.

Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.

Abstract: A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

Abstract: Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.

Abstract: A semiconductor device includes first and second global bit lines; first, second, third and fourth sense node; a first sense switch coupled between the first sense node and the first global bit line; a second sense switch coupled between the second sense node and the second global bit line; a third sense switch coupled between the third sense node and the first global bit line; a fourth sense switch coupled between the fourth sense node and the second global bit line; a first sense amplifier including a first terminal coupled to the first sense node and a second terminal coupled to the second sense node; a second sense amplifier including a third terminal coupled to the third sense node and a fourth terminal coupled to the fourth sense node. The first, second, third and fourth terminals respectively have first, second, third and fourth parasitic capacitances substantially equal in capacitance value.

Abstract: To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.

Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate, a word line, and an isolation region. The semiconductor substrate has an active region and first and second grooves. Each of the first and second grooves extends across the active region. The first groove is wider in width than the second groove. The word line is disposed in the first groove. The isolation region is disposed in the second groove. The isolation region is narrower in width than the word line.

Abstract: In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened.

Abstract: A semiconductor device manufacturing method is provided. First and second semiconductor chips are prepared, including first and second electrodes on first and second surfaces respectively. The second semiconductor chip includes a third electrode on a third surface opposite to the second surface. The third electrode overlaps the second electrode. The second surface includes an electrode-free region that is free of any electrode. A sealing resin is applied on the first surface of the first semiconductor chip. A second surface of the first semiconductor chip is held by a bonding tool including a pressing surface and a supporting-portion projected from the pressing surface. The pressing surface is made into contact with the second electrode. The supporting-portion is arranged at a position facing the electrode-free region. The second semiconductor chip is stacked over the first semiconductor chip by the bonding tool to electrically connect the third electrode to the first electrode.

Abstract: A semiconductor device includes a semiconductor substrate having a groove; a gate insulator; a first diffusion region; a gate electrode; a hydrogen-containing insulator; and a fluorine-containing insulator. The gate insulator covers inside surfaces of the groove. The first diffusion region is formed in the substrate. The first diffusion region has a first contact surface that contacts the gate insulator. The gate electrode is formed on the gate insulator and in the groove. The hydrogen-containing insulator is formed over the gate electrode and in the groove. The hydrogen-containing insulator is adjacent to the gate insulator. The fluorine-containing insulator is formed on the hydrogen-containing insulator and in the groove. The first contact surface includes Si—H bonds and Si—F bonds.

Abstract: Disclosed herein is a device that includes first and second logic circuits driving first and second output nodes, respectively. The first logic circuit includes first and second transistors that are coupled in series between the first output node and a power line, in which the first transistor is controlled to change between a conductive state and a non-conductive state and the second transistor is controlled to keep a conductive state. The second gate circuit includes third and fourth transistors that are coupled in series between the second output node and the power line, in which each of the third and fourth transistors is controlled to change between a conductive state and a non-conductive state.