Abstract: A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively.

Abstract: A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode materials are conductive molybdenum oxide.

Abstract: A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level.

Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin (<m) or highly doped so that it remains amorphous after subsequent anneal treatments. A second dielectric material is formed above the first dielectric material. The second dielectric material is sufficiently thick (>3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.

Abstract: Semiconductor device comprises a memory cell region, a peripheral region, and first wiring. The memory cell region includes a first isolation region, and a first active region provided so as to be divided off by the first isolation region. The peripheral region includes a second isolation region, and a second active region divided off by the first and second isolation regions and protruding from the upper surface of an insulating film located in the first and second isolation regions. The first wiring is buried in portions of a semiconductor substrate within the memory cell region and the peripheral region, so as to extend over the first and second active regions in a first direction. The first-direction width of the second active region is constant.

Abstract: A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.

Abstract: A semiconductor device that includes a semiconductor substrate. First and second mode registers are provided on the semiconductor substrate and store information, respectively. First and second circuits are provided on the semiconductor substrate. The first and second circuits have substantially the same configuration. The first and second circuits perform an operation in response to the information of the first and second mode registers, respectively.

Abstract: A semiconductor device includes a memory cell, a first bit line coupled to the memory cell, a second bit line, a first sense amplifier circuit including first and second transistors, the first transistor including a gate coupled to the first bit line, and the first and second transistors are coupled in series between the second bit line and a first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and supply a control signal to a gate of the second transistor.

Abstract: A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.

Abstract: A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.

Abstract: A silicon substrate having a first silicon oxide film formed via thermal oxidation and a second silicon oxide film formed via chemical vapor deposition and the like is subjected to preprocessing prior to selective epitaxial growth, wherein both the first and second silicon oxide films are etched with the same etching rate so as to completely remove the first silicon oxide film. Thus, it is possible to precisely control the sizes of contact holes formed in the silicon substrate, thus preventing contact plugs from short-circuiting with silicon epitaxial layers.

Abstract: A semiconductor device includes groove-like regions that are formed between two adjacent bit lines among a plurality of bit lines each having upper and side surfaces covered with a cap insulating film and a side-wall insulating film, respectively, a SiON film that contains more O (oxygen) than N (nitrogen) and continuously covers inner surfaces of the groove-like regions, and a silicon dioxide film formed by reforming polysilazane and filled in the groove-like regions with the SiON film interposed therebetween.

Abstract: Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.

Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).

Abstract: A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal provided to receive a command that communicates the data with an outside thereof, and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.

Abstract: A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.

Abstract: A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film.

Abstract: A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.

Abstract: A semiconductor device of the invention includes a first wiring layer including a signal wiring line formed therein, and a second wiring layer stacked on the first wiring layer and including a power-supply plane and/or ground plane formed therein, the power-supply plane or the ground plane is not formed at least within a part of the region of the second wiring layer facing the signal wiring line of the first wiring layer.

Abstract: A photomask has a mask blank and a light shielding film formed on the mask blank. The light shielding film includes a plurality of opening traces extending in a first direction. An end of a first opening trace in the first direction and an end of a second opening trace in the first direction are in different positions in the first direction. The second opening trace adjoins the first opening trace.