Abstract: A system includes a control chip and a plurality of command terminals receiving a plurality of command signals, respectively; a command decoder coupled to the command terminals, the command decoder being configured to output an internal command in response to the command signals; and a layer address buffer configured to output a layer address each time the command decoder outputs a row command as the internal command and outputs a column command as the internal command; and a plurality of core chips stacked with one another, each of the core chips being configured to receive the, row command and the layer address output together with the row command, to receive the column command and the layer address output together with the column command, and to free from receiving the command signals.

Abstract: A device includes a semiconductor substrate, a first penetration electrode and a plurality of second penetration electrodes each penetrating the semiconductor substrate, a first terminal and a plurality of second terminals formed on a one side of the substrate, and a third terminal and a plurality of fourth terminals formed on an opposite side of the substrate. Each of the first and third terminals is vertically aligned with and electrically connected to first penetration electrode. Each of the second terminals is vertically aligned with an associated one of the second penetration electrodes and electrically connected to another one of the second penetration terminals that is not vertically aligned with the associated second terminal. Each of fourth terminals is vertically aligned with and electrically connected to an associated one of the second penetration electrodes.

Abstract: Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.

Abstract: A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

Abstract: A method of manufacturing a semiconductor device comprises forming a contact hole within an interlayer insulating film of a substrate and forming a contact plug while the substrate is heated. In forming the contact plug, the substrate is held on a stage within the chamber of a sputtering apparatus through a chuck, and an ESC voltage applied to the chuck is increased stepwise in a plurality of steps. First target power is applied to a target within the chamber to form a first Al film in the contact hole. Next, second target power higher than the first target power is applied to the target within the chamber to form a second Al film on the first Al film.

Abstract: A semiconductor device includes first and second global bit lines; first, second, third and fourth sense node; a first sense switch coupled between the first sense node and the first global bit line; a second sense switch coupled between the second sense node and the second global bit line; a third sense switch coupled between the third sense node and the first global bit line; a fourth sense switch coupled between the fourth sense node and the second global bit line; a first sense amplifier including a first terminal coupled to the first sense node and a second terminal coupled to the second sense node; a second sense amplifier including a third terminal coupled to the third sense node and a fourth terminal coupled to the fourth sense node. The first, second, third and fourth terminals respectively have first, second, third and fourth parasitic capacitances substantially equal in capacitance value.

Abstract: A semiconductor device manufacturing method is provided. First and second semiconductor chips are prepared, including first and second electrodes on first and second surfaces respectively. The second semiconductor chip includes a third electrode on a third surface opposite to the second surface. The third electrode overlaps the second electrode. The second surface includes an electrode-free region that is free of any electrode. A sealing resin is applied on the first surface of the first semiconductor chip. A second surface of the first semiconductor chip is held by a bonding tool including a pressing surface and a supporting-portion projected from the pressing surface. The pressing surface is made into contact with the second electrode. The supporting-portion is arranged at a position facing the electrode-free region. The second semiconductor chip is stacked over the first semiconductor chip by the bonding tool to electrically connect the third electrode to the first electrode.

Abstract: In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened.

Abstract: To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.

Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate, a word line, and an isolation region. The semiconductor substrate has an active region and first and second grooves. Each of the first and second grooves extends across the active region. The first groove is wider in width than the second groove. The word line is disposed in the first groove. The isolation region is disposed in the second groove. The isolation region is narrower in width than the word line.

Abstract: A semiconductor device includes a semiconductor substrate having a groove; a gate insulator; a first diffusion region; a gate electrode; a hydrogen-containing insulator; and a fluorine-containing insulator. The gate insulator covers inside surfaces of the groove. The first diffusion region is formed in the substrate. The first diffusion region has a first contact surface that contacts the gate insulator. The gate electrode is formed on the gate insulator and in the groove. The hydrogen-containing insulator is formed over the gate electrode and in the groove. The hydrogen-containing insulator is adjacent to the gate insulator. The fluorine-containing insulator is formed on the hydrogen-containing insulator and in the groove. The first contact surface includes Si—H bonds and Si—F bonds.

Abstract: A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.

Abstract: A semiconductor device of the present invention includes: transistor Tr1 arranged on a semiconductor substrate; transistor Tr2 arranged such that a carrier drift direction thereof viewed on the semiconductor substrate is identical to a carrier drift direction of transistor Tr1; diffusion layer 51c connecting diffusion layers 51a and 51b on carrier supply sides of transistors Tr1 and Tr2; and contact plug 61 that is connected to a surface of diffusion layers 51a and 51b on the carrier supply sides of transistors Tr1 and Tr2 or that is connected to a surface of diffusion layer 51c connecting the diffusion layers to each other, and that supplies diffusion layers 51a and 51b with electricity.

Abstract: To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first counter that counts the first frequency dividing clock; a second counter that synchronizes with the second frequency dividing clock to fetch a count value of the first counter; and a selection circuit that exclusively selects count values of the first and second counters. According to the present invention, a relation of the count values between the first and second counters is kept always constant, and thus, even when hazard occurs, the count values are only made to jump and the count values do not fluctuate.

Abstract: A device includes a first region including a plurality of first memory elements and a plurality of first vertical transistors, the first vertical transistors comprising a plurality of first selective transistors and a first switching transistor, each of the first selective transistors including an upper electrode coupled to a corresponding one of the first memory elements and a lower electrode, the first switching transistor including an upper electrode and a lower electrode coupled in common to the lower electrodes of the first selective transistors through a first signal line, a second region arranged to make a first line with the first region in a first direction and including a plurality of second memory elements and a plurality of second vertical transistors, the second vertical transistors comprising a plurality of second selective transistors and a second switching transistor, and a third region sandwiched between the first and the second regions.

Abstract: A method of manufacturing a semiconductor device includes: supplying a supercritical fluid mixed with an under-fill material to a stacked unit, which has a plurality of stacked semiconductor chips; and filling the under-fill material in the space between the plurality of the semiconductor chips, by heating the stacked unit placed in the inside of the high-pressure vessel and curing the under-fill material flowing in the space between the plurality of the semiconductor chips by a polymerization reaction, while the supercritical fluid is being supplied.

Abstract: A semiconductor device includes a plurality of MOS transistors and wiring connected to a source electrode or a drain electrode of the plurality of MOS transistors and, the wiring being provided in the same layer as the source electrode and the drain electrode in a substrate, or in a position deeper than a surface of the substrate.

Abstract: FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the first and second selector transistors has a bias applied that releases the select transistors from an electrically floating state together with biasing each of the memory cell transistors.

Abstract: A semiconductor chip 109 is mounted on a substrate 100, first wire group 120 and a second wire group 118 having a wire length shorter than the first wire group are provided so as to connect the substrate 100 and the semiconductor chip 109 to each other, and a sealing resin 307 is injected from the first wire group 120 toward the second wire group 118 so as to form a sealer 401 covering the semiconductor chip 109, the first wire group 120, and the second wire group 118.

Abstract: For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.