Patents Assigned to Elpida Memory, Inc.
  • MASK-WRITE APPARATUS FOR A SRAM CELL
    Publication number: 20120224439
    Abstract: Disclosed herein is a device that comprises a SRAM cell, a pair of bit-lines coupled with the SRAM cell, a writing circuit producing at first and second output nodes thereof true and complementary data signals responsive to data to be written, a first pass transistor coupled between one of the pair of the bit-lines and the first output node of the writing circuit, a second pass transistor coupled between the other of the pair of bit lines and the second output node of the writing circuit; and a mask-write circuit configured to render both of the first and second pass transistors conductive in a write operation and render selected one or ones of first and second pass transistors non-conductive in a write-mask operation.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 6, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Giulio Martinozzi, Mauro Pagliato
  • Semiconductor device performing serial parallel conversion
    Patent number: 8259526
    Abstract: A first transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with first and second read data. A second transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with third and fourth read data. Outputs of the first and second transfer circuits are sequentially output from a multiplex circuit. When a first operation mode is selected, all the pipeline circuits are activated. When a second operation mode is selected, one of the pipeline circuits in the first transfer circuit and one of the pipeline circuits in the second transfer circuit are activated, whereas the others of the pipeline circuits are inactivated.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: September 4, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Takahiko Fukiage, Atsushi Shimizu
  • Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality
    Patent number: 8259509
    Abstract: A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: September 4, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Shetti Shanmukheshwara Rao, Ankur Goel
  • Semiconductor device and method of manufacturing the same
    Patent number: 8258630
    Abstract: A semiconductor device includes: a first layer; a second layer above the first layer; first and second multi-layered structures; and a supporter. The first and second multi-layered structures extend from the first layer to connect to the second layer. The supporter extends from the first layer to connect to the second layer. The supporter is between the first and second multi-layered structures. The supporter is separated from the first and second multi-layered structures by empty space.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: September 4, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Naoki Yokoi
  • Semiconductor memory device
    Patent number: 8259496
    Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: September 4, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Takeshi Ohgami
  • OUTPUT CIRCUIT FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE HAVING OUTPUT CIRCUIT, AND METHOD OF ADJUSTING CHARACTERISTICS OF OUTPUT CIRCUIT
    Publication number: 20120217992
    Abstract: To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.
    Type: Application
    Filed: May 10, 2012
    Publication date: August 30, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Hiroki FUJISAWA
  • SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF
    Publication number: 20120218845
    Abstract: Disclosed herein is a semiconductor device comprising an array having a hierarchical bit line structure, global bit lines adjacent to each other, local bit lines corresponding to the global bit lines, hierarchical switches, precharge circuits precharging the global bit lines, precharge circuits precharging the local bit lines, and a control circuit. When performing a test of the array, precharge voltages for the global bit lines are set to potentials different from each other, and the control circuit controls the potentials to be applied to the local bit lines through the global bit lines and the hierarchical switches.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 30, 2012
    Applicant: Elpida Memory Inc.
    Inventors: Shinichi TAKAYAMA, Kazuhiko KAJIGAYA
  • Method for producing low-film, semiconductor device, and method for manufacturing the same
    Patent number: 8253251
    Abstract: Hydrophobicity of a low dielectric constant film comprising a porous silica film is improved by applying a raw material for forming a porous silica film onto a substrate, and performing vapor-phase transport treatment to expose the substrate to an atmosphere of organic amine vapor to which no water is added. Simultaneously, reduction in a dielectric constant, reduction in leakage current, and improvement in mechanical strength are attained by controlling a pore diameter in a predetermined range.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 28, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshinori Cho, Takamaro Kikkawa
  • Semiconductor device and manufacturing method thereof
    Patent number: 8253254
    Abstract: A semiconductor device has a first insulation film defining a plurality of contact holes arranged along a predetermined direction. A plurality of first contact plugs is respectively formed in the contact holes. A second insulation film is formed on the first insulation film and defining an opening to expose a predetermined region of the first insulation film including a region where the first contact plugs are formed. A plurality of interconnections are formed to extend across the opening and to be in contact with top surfaces of the first contact plugs, respectively.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: August 28, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Shingo Ujihara
  • Filter circuit element and electronic circuit device
    Patent number: 8253029
    Abstract: A plurality of vias is disposed side by side on a multilayer board. A first via which is one of the vias disposed at one outer portion is electrically connected to a first outgoing line provided on the multilayer board. A second via at the other outer portion is electrically connected to a second outgoing line provided on the multilayer board. A plurality of the vias is connected to a first fixed potential layer (a ground layer, for example) of the multilayer board. At least one second fixed potential layer is provided, with a plurality of the vias through a clearance and having the same potential as that of the first fixed potential layer, as an inner layer of the multilayer board between the first and second outgoing lines and the fixed potential layer. Therefore, a BPF whose rate of occupied area is low is formed on the multilayer board without additional production processes.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: August 28, 2012
    Assignees: NEC Corporation, Elpida Memory, Inc.
    Inventors: Takashi Nakano, Masaharu Imazato, Yoji Nishio
  • Semiconductor device with hollow and throughhole and method of manufacturing same
    Patent number: 8253258
    Abstract: The present invention provides a semiconductor device which includes a semiconductor chip formed with an electrode pad on one surface thereof, a wiring board having a wiring pattern, with its one surface opposing the other surface of the semiconductor chip, a wire for electrically connecting the electrode pad of the semiconductor chip with the wiring pattern of the wiring board, an external terminal arranged on the other surface of the wiring board for electrical connection with the electrode pad through the wire and wiring pattern, and a sealant for fixing the semiconductor chip on one surface of the wiring board such that a hollow is formed between the other surface of the semiconductor chip and the one surface of the wiring board. The wiring board includes a throughhole communicating with the hollow.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: August 28, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Kaoru Sonobe, Hidehiro Takeshima, Shinei Sato
  • Semiconductor memory device having pad electrodes arranged in plural rows
    Patent number: 8254153
    Abstract: To include a first memory cell array area and a second memory cell array area, a peripheral circuit area arranged between these memory cell array areas, a first pad row arranged between the first memory cell array area and the peripheral circuit area, and a second pad row arranged between the second memory cell array area and the peripheral circuit area. No peripheral circuit is arranged substantially between the first memory cell array area and the first pad row as well as between the second memory cell array area and the second pad row. With this arrangement, a memory cell array area and a predetermined pad can be connected within a shorter distance by using a wiring formed in an upper layer that has a lower electrical resistance, and a power potential can be stably supplied to the memory cell array area.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: August 28, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Chiaki Dono, Hiroki Fujisawa
  • SEMICONDUCTOR DEVICE HAVING PLURAL PENETRATION ELECTRODES PENETRATING THROUGH SEMICONDUCTOR SUBSTRATE AND TESTING METHOD THEREOF
    Publication number: 20120212272
    Abstract: Disclosed herein is a device that includes first and second current paths, first and second latch circuits electrically connected to the first and second current paths, respectively, a driver circuit supplying first data to the first latch circuit, and supplying second data representing a logical value opposite to a logical value of the first data to the second latch circuit, a control circuit controlling the driver circuit to be alternately and repeatedly in a first period in which the driver circuit supplies the first data to the first latch circuit and does not supply the second data to the second latch circuit, and in a second period in which the driver circuit supplies the second data to the second latch circuit and does not supply the first data to the first latch circuit, and a monitor circuit.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 23, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Hideyuki YOKOU, Yasuyuki Shigezane
  • SEMICONDUCTOR DEVICE HAVING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE
    Publication number: 20120213021
    Abstract: Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 23, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Yoshiro Riho, Yoshio Mizukane, Hiromasa Noda
  • SEMICONDUCTOR DEVICE HAVING CALIBRATION CIRCUIT FOR ADJUSTING OUTPUT IMPEDANCE OF OUTPUT BUFFER CIRCUIT
    Publication number: 20120212254
    Abstract: Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 23, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Hideyuki YOKOU, Takanori Eguchi, Manabu Ishimatsu
  • SEMICONDUCTOR DEVICE THAT CAN CANCEL NOISE IN BIAS LINE TO WHICH BIAS CURRENT FLOWS
    Publication number: 20120212286
    Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 23, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Hideyuki YOKOU, Isao Nakamura, Manabu Ishimatsu
  • Stacked semiconductor device and fabrication method for same
    Patent number: 8247896
    Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: August 21, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Yutaka Kagaya, Hidehiro Takeshima, Masamichi Ishihara
  • Semiconductor device with refresh control circuit
    Patent number: 8248879
    Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: August 21, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Kiyohiro Furutani
  • Semiconductor device
    Patent number: 8248838
    Abstract: A semiconductor device includes a comparison unit for comparing a resistance value of a memory element selectively connected to an input terminal with a resistance value of a reference resistance, and a resistance reference unit capable of selecting one of a plurality of resistance values and capable of being selectively connected to the input terminal.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: August 21, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Yasuko Tonomura
  • Semiconductor device having hierarchically structured bit lines and system including the same
    Patent number: 8248834
    Abstract: To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: August 21, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Seiji Narui