Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic % and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

Abstract: A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO2) on the first TiN electrode; depositing a dielectric material on the first layer of titanium dioxide; and depositing a second TiN electrode on the dielectric material.

Abstract: A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO2) on the first TiN electrode; depositing a dielectric material on the first layer of titanium dioxide; and depositing a second TiN electrode on the dielectric material.

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is first etched and then annealed in a reducing atmosphere or an inert atmosphere to promote the formation of a desired crystal structure and to remove oxygen rich compounds. The binary metal compound may be a metal oxide. Etching the metal oxide (i.e. molybdenum oxide) may result in the removal of oxygen rich phases and the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer.

Abstract: Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node.

Abstract: A method for reducing leakage current in DRAM capacitor stacks by introducing dielectric interface layers between the electrodes and the bulk dielectric material. The dielectric interface layers are typically amorphous dielectric materials with a k value between about 10 and about 30 and are less than about 1.5 nm in thickness. Advantageously, the thickness of each of the dielectric interface layers is less than 1.0 nm. In some cases, only a single dielectric interface layer is used between the bulk dielectric material and the second electrode.

Abstract: A semiconductor device includes a data transmission line and a data transmission line precharge circuit. The data transmission line precharge circuit sets a precharge potential of the data transmission line to a first potential at the time of a first write mode in which data masking is not performed. The data transmission line precharge circuit sets the precharge potential to a potential different from the first potential at the time of a second write mode in which data masking is performed. When data masking is not carried out, precharging to a potential at which data can be written in excellent fashion can be performed. When data masking is carried out, precharging to a potential that inhibits a fluctuation in bit-line potential can be performed.

Abstract: A level shift circuit includes: a pair of first and second P-channel transistors which are connected in a flip-flop manner and whose sources connected to a first power supply line; a pair of first and second N-channel transistors with the first N-channel transistor provided between the first P-channel transistor and a second power supply line and the second N-channel transistor provided between the second P-channel transistor and the second power supply line, in which input signals complementary to each other are inputted to their gates; and a current supply circuit provided between the first power supply line and a drain of the first N-channel transistor and between the first power supply line and a drain of the second N-channel transistor, respectively.

Abstract: A system that includes a first semiconductor chip, a second semiconductor chip, and a controller chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit.

Abstract: A semiconductor device according to the present invention includes plural controlled chips CC0 to CC7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A13 to A15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A13 to A15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A13 to A15 reach the controlled chips earlier than the command signal ICMD.

Abstract: There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, and a drain region; a first inter-layer insulation film covering the transistor; a first contact plug formed penetrating through the first inter-layer insulation film and connected to either the source region or the drain region; a second inter-layer insulation film covering the first contact plug; a groove extending in the second inter-layer insulation film in a same direction as an extending direction of the gate electrode and exposing a top surface of the first contact plug at a bottom thereof; a second contact plug connected to the first contact plug and formed in the groove; and a wiring pattern extending on the second inter-layer insulation film so as to traverse the groove and integrated with the second contact plug.

Abstract: A semiconductor device includes a plurality of semiconductor memories, a clock signal synchronization circuit, and a first circuit. The clock signal synchronization circuit is electrically coupled to the plurality of semiconductor memories. The first circuit is electrically coupled to the plurality of semiconductor memories. The first circuit changes a bit width of data. The data is transferred between the first circuit and the plurality of semiconductor memories.

Abstract: A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern (14x) linearly extending in a first direction and a second support pattern (14y) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.

Abstract: A device includes a semiconductor region surrounded with the isolation region and includes a first active region, a channel region and a second active region arranged in that order in a first direction. A first side portion of the first active region and a second side portion of the second active region faces each other across a top surface of the channel region in the first direction. A gate electrode covers the top surface and the first and second side portions and extends in a second direction that intersects the first direction. A first diffusion layer is formed in the first active region. A second diffusion layer is formed in the second active region. An embedded contact plug is formed in the first active region and extends downwardly from the upper surface of the semiconductor region and contacts with the first diffusion layer.

Abstract: A semiconductor device includes: a cell gate trench with a bottom face and first/second side faces; a field-shield gate trench narrower than the cell gate trench; a first upper diffusion layer between the cell gate trench and the field-shield gate trench; a second upper diffusion layer on the opposite side of the cell gate trench from the first upper diffusion layer; a third upper diffusion layer on the opposite side of the field-shield gate trench from the first upper diffusion layer; a lower diffusion layer on the bottom face of the cell gate trench; first and second storage elements electrically connected to the first and second upper diffusion layers, respectively; a bit line electrically connected to the lower diffusion layer; a word line covering first and second side faces via a gate insulating film; and a field-shield gate electrode in the field-shield gate trench via a gate insulating film.

Abstract: A semiconductor device includes an antifuse element. The semiconductor device includes a first well of a first conductivity type disposed in a semiconductor substrate; a first insulating film on the first well; a first conductive film of the first conductivity type on the first insulating film; and an impurity-introduced region of the first conductivity type. The impurity-introduced region of the first conductivity type in the first well is higher in impurity concentration than the first well. The impurity-introduced region includes a first portion that faces toward the first conductive film through the first insulating film.

Abstract: An internal voltage adjusting circuit of a semiconductor memory device processes a period from activation to deactivation of a reset bar signal by dividing the period into a first period to a third period. In the first period, a peripheral circuit voltage is stabilized to a lowest value to suppress power consumption. In the second period in which a power source voltage is stabilized, the peripheral circuit voltage is set to a highest value to read out optimum internal voltage values from a fuse circuit in a stable manner. In the third period after reading out the optimum internal voltage values, the peripheral circuit voltage is returned to the lowest value to suppress the power consumption. When the reset bar signal is deactivated, the peripheral circuit voltage is set based on the optimum internal voltage values read out from the fuse circuit.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes preparing a wafer having a plurality of chip areas, each chip area to become semiconductor chip, bonding the first side of the wafer to a support substrate through a removable adhesive, dividing the wafer into individually separate semiconductor chips, applying adhesive tape to the second side of the separate semiconductor chips, the second side being opposite to the first side bonded to the support substrate, and the adhesive tape being softer than the support substrate, removing the support substrate from the semiconductor chips, and picking up the separate semiconductor chips that are on the adhesive tape.

Abstract: A semiconductor device includes a gate electrode on a gate insulating film over a semiconductor substrate, a first sidewall insulating film on a side surface of the gate electrode, and source and drain regions, each including a pocket diffusion layer of a first conductivity type, and first and second diffusion layers of a second conductivity type. The pocket diffusion layer is disposed in the semiconductor substrate. The first diffusion layer of a second conductivity type extends over the pocket diffusion layer. The first diffusion layer faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer over the first diffusion layer is higher in impurity concentration than the first diffusion layer. The second diffusion layer is separated by the first diffusion layer from the pocket diffusion layer, and has a side surface which faces toward the first sidewall insulating film through the first diffusion layer.

Abstract: A solid memory may include a recording layer including Ge, Sb and Te as major components. The recording layer may include a superlattice. The recording layer may include multi-layers each having a parent phase showing a phase transformation in solid-states, the phase transformation causing change in electrical property of the recording layer. The recording layer may include an Sb2Te3 layer that includes at least one period of a first lamination of a first Te-atomic layer, a first Sb-atomic layer, a second Te-atomic layer, a second Sb-atomic layer, and a third Te-atomic layer in these order, a GeTe layer that includes at least one period of a second lamination of a fourth Te-atomic layer and a Ge-atomic layer, and an Sb layer that includes a plurality of Sb-atomic layers.