Patents Assigned to Elpida Memory, Inc.
-
Publication number: 20130052790Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a doped material formed from a first dopant in concert with a second dopant wherein the second dopant has a different physical size from the first dopant and the presence of the second dopant influences the solubility of the first dopant in the dielectric material.Type: ApplicationFiled: August 29, 2011Publication date: February 28, 2013Applicants: ELPIDA MEMORY, INC., INTERMOLECULAR, INC.Inventors: Wim Deweerd, Hanhong Chen, Hiroyuki Ode
-
Publication number: 20130049223Abstract: The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.Type: ApplicationFiled: August 16, 2012Publication date: February 28, 2013Applicant: Elpida Memory, Inc.Inventors: Keisuke NOMOTO, Toru ISHIKAWA
-
Publication number: 20130052792Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.Type: ApplicationFiled: August 29, 2011Publication date: February 28, 2013Applicants: ELPIDA MEMORY, INC., INTERMOLECULAR, INC.Inventors: Sandra Malhotra, Wim Deweerd, Hanhong Chen, Xiangxin Rui, Hiroyuki Ode, Mitsuhiro Horikawa, Kenichi Koyanagi
-
Publication number: 20130051160Abstract: Disclosed herein is a device that includes a memory cell array having short and long sides, a row decoder, a row fuse circuit, a column decoder and a column fuse circuit. The row decoder, the row fuse circuit and the column fuse circuit are arranged along the long side of the memory cell array. The column decoder is arranged along the short side of the memory cell array.Type: ApplicationFiled: August 24, 2012Publication date: February 28, 2013Applicant: Elpida Memory, Inc.Inventor: Tatsuo SAWADA
-
Patent number: 8383511Abstract: Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger by a length X than diameter of the opening in the first mask layer. Thereafter, mask material is formed into the opening in the second mask layer, to form a cavity with a diameter X within the opening in the second mask layer. There is formed a mask which includes the second mask layer and the mask material having therein opening including the cavity.Type: GrantFiled: February 15, 2012Date of Patent: February 26, 2013Assignee: Elpida Memory, Inc.Inventor: Mitsunari Sukekawa
-
Patent number: 8384432Abstract: A semiconductor device includes a plurality of core chips and an interface chip stacked together. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and a bidirectional buffer circuit that drives the through silicon vias. The interface chip also includes a logic-level holding circuit that holds a logic level of the through silicon vias. The bidirectional buffer circuit includes an input buffer and an output buffer. The driving capability of a first inverter of the logic-level holding circuit is smaller than the driving capability of the output buffer of the bidirectional buffer circuit.Type: GrantFiled: October 8, 2010Date of Patent: February 26, 2013Assignee: Elpida Memory, Inc.Inventor: Chikara Kondo
-
Patent number: 8384143Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.Type: GrantFiled: March 30, 2012Date of Patent: February 26, 2013Assignee: Elpida Memory, Inc.Inventor: Toshiyuki Hirota
-
Patent number: 8385139Abstract: A semiconductor device includes an input buffer that receives an address signal having a first amplitude, a level shifter that converts an amplitude of the address signal output from the input buffer to a second amplitude that is smaller than the first amplitude, an address controller that receives the address signal output from the level shifter, address decoders that generate a decode signal by decoding the address signal output from the address controller, and level shifters that convert an amplitude of the address signal or of the decode signal from the second amplitude to the first amplitude such that at least an amplitude level of the decode signal becomes the first amplitude.Type: GrantFiled: September 10, 2010Date of Patent: February 26, 2013Assignee: Elpida Memory, Inc.Inventor: Chiaki Dono
-
Patent number: 8384433Abstract: To include a first inverter that receives an input signal to output an inverted signal, a second inverter that receives the inverted signal to output a first internal signal, and a third inverter that receives the input signal and outputs a second internal signal by using the inverted signal as a power supply. According to the present invention, because a signal on one signal path is used as a power supply of an inverter included in the other signal path, phases of a pair of output signals based on the input signal can be exactly matched without adding a capacitor or a resistor for adjustment.Type: GrantFiled: April 11, 2011Date of Patent: February 26, 2013Assignee: Elpida Memory, Inc.Inventors: Takenori Sato, Hideaki Kato
-
Publication number: 20130045582Abstract: A capacitor insulating film may include, but is not limited to, strontium, titanium, and oxygen. The capacitor insulating film has a ratio of a spectrum intensity of (200) crystal face of the capacitor insulating film to a spectrum intensity of (111) crystal face of the capacitor insulating film in the range of 1.0 to 2.3. Each of the spectrum intensities of (200) crystal face and (111) crystal face is measured by an X-ray diffraction method.Type: ApplicationFiled: October 25, 2012Publication date: February 21, 2013Applicant: ELPIDA MEMORY, INC.Inventor: Elpida Memory, Inc.
-
Publication number: 20130043596Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.Type: ApplicationFiled: October 19, 2012Publication date: February 21, 2013Applicant: Elpida Memory, Inc.Inventor: Elpida Memory, Inc.
-
Patent number: 8379479Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.Type: GrantFiled: June 5, 2012Date of Patent: February 19, 2013Assignee: Elpida Memory, Inc.Inventor: Atsuo Koshizuka
-
Patent number: 8381157Abstract: A device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a plurality of first data signals in response to data stored in selected ones of the first memory cells, a plurality of first data electrodes, and a first data control circuit coupled to the first control logic circuit and the first data electrodes. A second semiconductor chip includes a second memory cell array including a plurality of second memory cells, a second control logic circuit accessing the second memory cell array and producing a plurality of second data signals in response to data stored in selected ones of the second memory cells. The second control logic circuit is configured to store second timing adjustment information and to produce a second output timing signal.Type: GrantFiled: January 30, 2012Date of Patent: February 19, 2013Assignee: Elpida Memory, Inc.Inventors: Naohisa Nishioka, Chikara Kondo
-
Patent number: 8378499Abstract: A semiconductor storage device with active regions formed in the shape of a band in a substrate; a plurality of word lines arranged at equal intervals that intersect the active regions; cell contacts that includes first cell contacts in the active regions in the center portions in a longitudinal direction, and second cell contacts at both ends in the longitudinal direction; bit line contacts on the first cell contacts; bit lines that pass over the bit line contacts; storage node contacts on the second cell contacts; storage node contact pads on the storage node contacts; and storage capacitors on the storage node contact pads. The center positions of the storage node contacts are offset from the center positions of the second cell contacts. The center positions of the storage node contact pads are offset from the center positions of the storage node contacts.Type: GrantFiled: December 6, 2011Date of Patent: February 19, 2013Assignee: Elpida Memory, Inc.Inventor: Eiji Hasunuma
-
Patent number: 8378417Abstract: A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element supplies potential to the well, the first element being in the well. The first element may include, but is not limited to, a first pillar body of the first conductivity type. The first pillar body has an upper portion that includes a first diffusion layer of the first conductivity type. The first diffusion layer is greater in impurity concentration than the well. The first vertical transistor is in the well. The first vertical transistor may include a second pillar body of the first conductivity type. The second pillar body has an upper portion that includes a second diffusion layer of a second conductivity type.Type: GrantFiled: March 31, 2010Date of Patent: February 19, 2013Assignee: Elpida Memory, Inc.Inventors: Kazuo Ogawa, Yoshihiro Takaishi
-
Patent number: 8378507Abstract: A wiring substrate and a semiconductor chip mounted on the wiring substrate are connected together via a bonding wire. The distance from each end of the semiconductor chip to a wire bond pad provided on the wiring substrate is smaller than the height of the semiconductor chip.Type: GrantFiled: October 2, 2009Date of Patent: February 19, 2013Assignee: Elpida Memory, Inc.Inventors: Satoshi Itaya, Dai Sasaki, Mitsuaki Katagirl
-
Patent number: 8381070Abstract: To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained.Type: GrantFiled: November 17, 2009Date of Patent: February 19, 2013Assignee: Elpida Memory, Inc.Inventor: Tetsuya Arai
-
Patent number: 8378415Abstract: A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions of the main pillar and made from a first-conduction-type material, a body layer that is formed at an intermediate portion of the main pillar sandwiched between the source and drain diffused layers and made from the first-conduction-type material, and a front gate electrode that is formed on a lateral face of the main pillar while placing a gate insulating film therebetween. Moreover, a back gate electrode made from a second-conduction-type material is formed in a pillar shape penetrating from an upper portion to a lower portion on an inner side of the main pillar.Type: GrantFiled: July 31, 2008Date of Patent: February 19, 2013Assignee: Elpida Memory, Inc.Inventor: Toshiyuki Higashino
-
Publication number: 20130039112Abstract: In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other.Type: ApplicationFiled: October 17, 2012Publication date: February 14, 2013Applicant: ELPIDA MEMORY, INC.Inventor: ELPIDA MEMORY, INC.
-
Publication number: 20130039118Abstract: A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence, and the second voltage has a temperature dependence opposite to that of a forward voltage of the diode. The control circuit detects a resistance state of the memory element in accordance with a change in current flowing in the memory cell in a state where the first/second voltage is applied to the first/second in a read operation of the memory cell.Type: ApplicationFiled: October 10, 2012Publication date: February 14, 2013Applicant: ELPIDA MEMORY INC.Inventor: Elpida Memory Inc.
