Patents Assigned to Elpida Memory, Inc.
  • METHOD FOR ALD DEPOSITION RATE ENHANCEMENT
    Publication number: 20120309162
    Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2?x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 6, 2012
    Applicants: Elpida Memory, Inc., Intermolecular, Inc.
    Inventors: Hanhong Chen, Sandra Malhotra, Hiroyuki Ode, Xiangxin Rui
  • MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE, AND WIRING SUBSTRATE
    Publication number: 20120306531
    Abstract: A semiconductor device includes a first input terminal receiving a termination resistance control signal, and a termination resistance circuit that is able to be controlled to be turned on or off by the termination resistance control signal. The termination resistance circuit is turned off, irrespective of a level of said termination resistance control signal when the semiconductor device outputs data in response to a read command.
    Type: Application
    Filed: August 20, 2012
    Publication date: December 6, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Atsuo Koshizuka
  • SEMICONDUCTOR DEVICE HAVING DUMMY PATTERN AND DESIGN METHOD THEREOF
    Publication number: 20120306106
    Abstract: Disclosed herein is the semiconductor substrate, wiring patterns and dummy patterns. A margin region is formed around the wiring pattern. The dummy region is further formed around the margin region. The dummy patterns are formed in the dummy region. The dummy patterns are arranged along the extending direction of the dummy region. Margin regions and dummy regions are allocated alternately with respect to the wiring pattern.
    Type: Application
    Filed: May 23, 2012
    Publication date: December 6, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Yorio TAKADA
  • SEMICONDUCTOR DEVICE HAVING REDUNDANT SELECT LINE TO REPLACE REGULAR SELECT LINE
    Publication number: 20120307578
    Abstract: Disclosed herein is a semiconductor device that includes a plurality of normal memory cells, a plurality of first normal lines each coupled to corresponding one or ones of the normal memory cells, a plurality of redundant memory cells, and first and second redundant lines each coupled to corresponding one or ones of the redundant memory cells. The first redundant line is configured to replace selected one or ones of the normal lines and the second line is configure to replace any one of the selected one or ones of the normal lines and remaining one or ones of the normal lines.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 6, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Hidekazu NOGUCHI
  • Semiconductor memory device and method of controlling auto-refresh
    Patent number: 8325550
    Abstract: Auto-refresh of a semiconductor device may be controlled by setting the number of auto-refresh to be performed in a period of time, based on temperature, when an auto-refresh command is detected.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: December 4, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiro Teramoto
  • Mode register output circuit
    Patent number: 8325537
    Abstract: To provide a semiconductor memory device including a mode register in which a mode signal is set, a data amplifier that amplifies read data read from a memory cell array, a data bus onto which the read data amplified by the data amplifier is transmitted, a data input/output circuit that outputs a signal on the data bus to outside, and a mode signal output circuit that outputs the mode signal set in the mode register onto the data bus. Because the mode signal is not caused to interrupt halfway along the data input/output circuit, but supplied onto the data bus that connects the data amplifier to the data input/output circuit, no collision of the read data with the mode signal occurs in the data input/output circuit.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: December 4, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Atsushi Shimizu, Takahiko Fukiage
  • Sense amplifier circuit and semiconductor device
    Patent number: 8320208
    Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: November 27, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Yasutoshi Yamada
  • Semiconductor integrated circuit device
    Patent number: 8320155
    Abstract: A memory device including memory cells each have two transistors and one storage element connected in series in this order between a corresponding one of bit lines and a constant voltage. The two transistors respectively have gate electrodes respectively connected to a corresponding one of first word lines and a corresponding one of second word lines. A memory array includes mats each having the memory cells disposed at all intersections between the bit lines and the first word lines, sense amplifiers each input with a corresponding pair of the bit lines in the same mat as a bit line pair, and first and second word drivers adapted to activate the first and second word lines, respectively.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: November 27, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Ryota Suzuki, Kazuteru Ishizuka
  • SEMICONDUCTOR DEVICE HAVING CHIP CRACK DETECTION STRUCTURE
    Publication number: 20120292759
    Abstract: A device includes a semiconductor substrate, a first penetration electrode and a plurality of second penetration electrodes each penetrating the semiconductor substrate, a first terminal and a plurality of second terminals formed on a one side of the substrate, and a third terminal and a plurality of fourth terminals formed on an opposite side of the substrate. Each of the first and third terminals is vertically aligned with and electrically connected to first penetration electrode. Each of the second terminals is vertically aligned with an associated one of the second penetration electrodes and electrically connected to another one of the second penetration terminals that is not vertically aligned with the associated second terminal. Each of fourth terminals is vertically aligned with and electrically connected to an associated one of the second penetration electrodes.
    Type: Application
    Filed: May 1, 2012
    Publication date: November 22, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Toru ISHIKAWA
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20120295415
    Abstract: A method of manufacturing a semiconductor device, comprising bonding a first principal surface of a substrate to a supporting substrate through a light-to-heat conversion film, and removing a portion of the light-to-heat conversion film exposed on the supporting substrate. A method of manufacturing a semiconductor device, comprising forming a light-to-heat conversion film on a supporting substrate, bonding a semiconductor substrate to the supporting substrate, so that the light-to-heat conversion film extends outside the semiconductor substrate, performing an anti-contamination treatment on the light-to-heat conversion film, and separating the supporting substrate and the semiconductor substrate from each other.
    Type: Application
    Filed: May 1, 2012
    Publication date: November 22, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Kenta ONO
  • Transmission method, transmission circuit and transmission system
    Patent number: 8315331
    Abstract: A transmission method for transmitting transmission data via a single line, includes: transmitting, as the transmission data, data that has one rising or falling transition of the amplitude of the data in each clock cycle of a clock and that carries a 2- or greater-bit value, making use of the phase from the edge of the clock to the transition in amplitude of the data.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: November 20, 2012
    Assignees: NEC Corporation, Elpida Memory, Inc.
    Inventors: Hideaki Saito, Hiroaki Ikeda
  • Chemical mechanical polishing apparatus
    Patent number: 8313359
    Abstract: A chemical mechanical polishing apparatus includes a container, a platen, first and second brushes, a polishing pad, a carrier, and a slurry supplier. The container has a bottom wall and a side wall. The side wall has an inwardly-extending upper portion. The platen is supported over the bottom wall. The platen is positioned lower than the inwardly-extending upper portion. The first brush brushes the side wall. The first brush is fixed to a side surface of the platen. The second brush brushes a side surface of the platen. The second brush is fixed to the bottom wall. The polishing pad is attached to the platen. The carrier presses a workpiece to be polished against the polishing pad. The slurry supplier supplies a slurry onto the polishing pad.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: November 20, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiya Saito
  • METHOD AND CIRCUIT TO DISCHARGE BIT LINES AFTER AN ERASE PULSE
    Publication number: 20120287723
    Abstract: Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path.
    Type: Application
    Filed: May 10, 2011
    Publication date: November 15, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Marco Passerini, Simone BARTOLI, Osama Khouri
  • Semiconductor device and method of forming the same
    Patent number: 8310002
    Abstract: A semiconductor device includes a semiconductor substrate, a first diffusion region, a gate insulating film, a gate electrode, a second diffusion region and a contact plug. The semiconductor substrate includes a base and at least a pillar. The first diffusion region is disposed in the base. The gate insulating film covers a side surface of the pillar. The gate electrode is separated from the pillar by the gate insulating film. The second diffusion region is disposed in an upper portion of the pillar. The contact plug is connected to the second diffusion region. The contact plug is connected to the entirety of the top surface of the pillar.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Fujimoto
  • Semiconductor device having plural semiconductor chips laminated to each other
    Patent number: 8310382
    Abstract: In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Akira Ide, Ryuji Takishita
  • Semiconductor memory device having diode cell structure
    Patent number: 8310865
    Abstract: A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence, and the second voltage has a temperature dependence opposite to that of a forward voltage of the diode. The control circuit detects a resistance state of the memory element in accordance with a change in current flowing in the memory cell in a state where the first/second voltage is applied to the first/second in a read operation of the memory cell.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory Inc.
    Inventor: Shuichi Tsukada
  • Semiconductor memory device and method of testing the same
    Patent number: 8310890
    Abstract: A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the device perform a first operation. The frequency of the clock signal is changed from the first frequency to a second frequency higher than the first frequency. The device performs the first operation in synchronization with the clock signal of the second frequency following changing the frequency of the clock signal.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Akiyoshi Yamamoto
  • Semiconductor device
    Patent number: 8310855
    Abstract: In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Yoshiro Riho
  • Semiconductor device having single-ended sensing amplifier
    Patent number: 8310887
    Abstract: A semiconductor device includes a bit line, a memory cell coupled to the bit line, the memory cell being configured such that a current flowing there the memory cell is varied in accordance with information stored M the memory cell, a first transistor coupled at a control electrode thereof to the bit line, a second transistor coupled to the bit line and supplied at a control electrode thereof with a first control signal, a global bit line, and a third transistor coupled in series with the first sistor between a node and the global bit line, the third transistor supplied at a control electrode thereof with a second control signal.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiko Kajigaya
  • Semiconductor memory device and data processing system including the semiconductor memory device
    Patent number: 8310897
    Abstract: A semiconductor device, includes a first memory cell array, a second memory cell array, a command decoder configured to produce a transfer command to transfer a data stored in a first area of the first memory cell array to a second area of the second memory cell array, when receiving a read command to the first memory cell array and sequentially a write command to the second cell memory array, a first address generator configured to produce a first internal address for designating the first area of the first memory cell array when receiving the transfer command from the command decoder; and a second address generator configured to produce a second internal address for designating the second area of the second memory cell array when receiving the transfer command from the command decoder.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: November 13, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Yoshinori Matsui