Abstract: A method of forming a dielectric film including a zirconium oxide film includes: forming a zirconium oxide film on a substrate to be processed by supplying a zirconium material and an oxidant, the zirconium material including a Zr compound which includes a cyclopentadienyl ring in a structure, and forming a titanium oxide film on the zirconium oxide film by supplying a titanium material and an oxidant, the titanium material including a Ti compound which includes a cyclopentadienyl ring in a structure.

Abstract: A semiconductor device is provided with the variable resistance element, and a control circuit that controls a resistance state of the variable resistance element by controlling current between a first end and a second end of the variable resistance element. The control circuit causes the variable resistance element to change from a first resistance state to a second resistance state by having a first current flow from the first end to the second end of the variable resistance element. In addition, after a second current smaller than the first current is made to flow from the first end to the second end of the variable resistance element, the control circuit causes the variable resistance element to change from the second resistance state to the first resistance state by having a third current flow from the second end to the first end thereof.

Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes.

Abstract: A method for reducing leakage current in DRAM capacitor stacks by introducing dielectric interface layers between the electrodes and the bulk dielectric material. The dielectric interface layers are typically amorphous dielectric materials with a k value between about 10 and about 30 and are less than about 1.5 nm in thickness. Advantageously, the thickness of each of the dielectric interface layers is less than 1.0 nm. In some cases, only a single dielectric interface layer is used between the bulk dielectric material and the second electrode.

Abstract: A semiconductor random access memory device includes a memory cell including a resistor whose resistance varies by formation and disappearance of a filament due to an oxidation-reduction reaction of metal ions, a memory area configured to include a first memory area operable in a nonvolatile mode in which a stored content thereof is not lost by a power-off event, and a second memory area operable in a volatile mode in which the stored content thereof is lost by the power-off event, each of the first memory area and the second memory area including the plurality of the memory cells, a register circuit that stores information including a first address information indicating the first memory area, and a second address information indicating the second memory area, and a control circuit that controls the nonvolatile mode, and the volatile mode, with reference to the information stored in the register circuit.

Abstract: Disclosed herein is a device that includes first and second current paths, first and second latch circuits electrically connected to the first and second current paths, respectively, a driver circuit supplying first data to the first latch circuit, and supplying second data representing a logical value opposite to a logical value of the first data to the second latch circuit, a control circuit controlling the driver circuit to be alternately and repeatedly in a first period in which the driver circuit supplies the first data to the first latch circuit and does not supply the second data to the second latch circuit, and in a second period in which the driver circuit supplies the second data to the second latch circuit and does not supply the first data to the first latch circuit, and a monitor circuit.

Abstract: Disclosed herein is a device that includes first and second ports arranged in a first direction and first and second circuits arranged between the first and second ports. The first and second ports are coupled to the first and second circuits, respectively. The first and second circuits include first and second sub circuits that control an operation timing thereof based on a timing signal, respectively. The control signal is transmitted through a control line extending in a second direction. Distances between the control line and the first and second sub circuits in the first direction are the same as each other. A coordinate of the control line in the first direction is different from an intermediate coordinate between coordinates of the first and second ports in the first direction.

Abstract: A current source includes a first MOS transistor of a first channel type including a drain connected to an output terminal, and a source directly connected to a first power supply, a second MOS transistor of the first channel type including a drain connected to a gate, the gate of the second MOS transistor being connected to the gate of the first transistor, and a source directly connected to the first power supply, a third MOS transistor of a second channel type opposite the first channel type including a drain connected to the drain of the second MOS transistor, a fourth MOS transistor of the second channel type including a drain connected to the source of the third MOS transistor, a gate connected to a first bias voltage, and a source directly connected to second power supply voltage, and a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third MOS transistor.

Abstract: A semiconductor device includes a semiconductor substrate, an impurity region in the semiconductor substrate, and a conductive layer contacting a top surface of the impurity region and at least a side surface of the impurity region.

Abstract: To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Abstract: A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.

Abstract: A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers.

Abstract: A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.

Abstract: A semiconductor device includes a semiconductor substrate including a fin. The fin includes first and second fin portions. The first fin portion extends substantially in a horizontal direction to a surface of the semiconductor substrate. The second fin portion extends substantially in a vertical direction to the surface of the semiconductor substrate. The fin has a channel region.

Abstract: A semiconductor device comprises a semiconductor substrate; an element-forming region that includes semiconductor elements formed on the semiconductor substrate; a buried electrode plug formed so as to penetrate through the semiconductor substrate; and a trench-type electrode that is buried in a trench within the semiconductor substrate positioned between the element-forming region and the buried electrode plug.

Abstract: A bit memory circuit of an antifuse element set includes two antifuse elements of which logical states are changed from an insulation state to a conductive state when a program voltage is applied. 1-bit data is represented by the logical states of the two antifuse elements. The two antifuse elements are collectively controlled by one decoder circuit. When writing data, the decoder circuit simultaneously performs insulation-breakdown on the two antifuse elements by simultaneously connecting the two antifuse elements to program voltage lines, respectively.

Abstract: A semiconductor device is provided with: a delay circuit including a first delay unit that has a plurality of differential first delay elements which are respectively connected in series, a plurality pairs of first contacts which are respectively provided between the plurality of first delay elements, and a first output circuit that outputs a first delayed signal corresponding to a pair of first contacts selected from among the plurality pairs of first contacts, on receiving a first selection signal; a second delay unit that receives the first delayed signal, and that includes a plurality of single-ended second delay elements which are respectively connected in series, a plurality of second contacts which are respectively provided between the plurality of second delay elements, and a second output circuit that outputs a second delayed signal corresponding to a second contact selected from among the plurality of second contacts, on receiving a second selection signal; and a control circuit that outputs each of

Abstract: A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.

Abstract: Disclosed herein is a device that includes a plurality of stacked core chips and an interface chip that controls the core chips. Each of the core chips includes a memory cell array, a penetration electrode, and an output circuit that outputs read data that are read from the memory cell array to the penetration electrode. The penetration electrode respectively provided in the core chips are commonly connected with each other, and the output circuits respectively provided in the core chips are activated in response to a read clock signal supplied from the interface chip.

Abstract: Such a device is disclosed that includes a first chip outputting a bank address signal and an active signal, and a plurality of second chips stacked on the first chip. Each of the second chips includes a plurality of memory banks each selected based on the bank address signal. Selected one or ones of the memory banks is brought into an active state in response to the active signal. Each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state. The first chip activates a bank active signal when at least one of the local bank active signals is activated.