Patents Assigned to Elpida Memory, Inc.
  • SYSTEMS AND METHODS FOR ERASING CHARGE-TRAP FLASH MEMORY
    Publication number: 20140071760
    Abstract: FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the first and second selector transistors has a bias applied that releases the select transistors from an electrically floating state together with biasing each of the memory cell transistors.
    Type: Application
    Filed: November 12, 2013
    Publication date: March 13, 2014
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Diego DELLA MINA, Chiara MISSIROLI, Osama KHOURI
  • SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME
    Publication number: 20140073127
    Abstract: A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure.
    Type: Application
    Filed: November 16, 2013
    Publication date: March 13, 2014
    Applicant: Elpida Memory, Inc.
    Inventors: Satoshi Itaya, Kayoko SHIBATA, Shoji AZUMA, Akira IDE
  • SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20140063992
    Abstract: A semiconductor device includes a plurality of memory cell arrays each including a plurality of memory cells and a first bit line coupled to the memory cells, a second bit line, a first voltage line, a plurality of first sense amplifiers each including a first transistor of which a gate is coupled to the first bit line of a corresponding one of the memory cell arrays and a second transistor, the first and second transistors in each of the first sense amplifiers being coupled in series between the second bit line and the first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and to supply a control signal to the gate of each of the second transistors.
    Type: Application
    Filed: November 5, 2013
    Publication date: March 6, 2014
    Applicant: ELPIDA MEMORY, INC
    Inventor: Soichiro YOSHIDA
  • Semiconductor device that can cancel noise in bias line to which bias current flows
    Patent number: 8665008
    Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: March 4, 2014
    Assignee: Elpida Memory, Inc.
    Inventors: Hideyuki Yokou, Isao Nakamura, Manabu Ishimatsu
  • Semiconductor device having hierarchically structured bit lines and system including the same
    Patent number: 8665625
    Abstract: A system includes a first circuit, a second circuit including a logic circuit, and a bus interconnecting the first and second circuits to each other so that the second circuit accesses the first circuit to perform a data transfer therebetween, wherein the first circuit includes a first sense amplifier array including a plurality of first sense amplifiers that are arranged in a first direction, each of the first sense amplifiers including first and second nodes; and a plurality of first global bit lines each extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that each of the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 4, 2014
    Assignee: Elpida Memory, Inc.
    Inventor: Seiji Narui
  • Semiconductor device
    Patent number: 8665641
    Abstract: A memory cell changes a potential of a bit line to a discharge potential from a precharge potential in correspondence with held data. A sense amplifier precharges a bit line by a precharge circuit, compares potential at a decision point linked with the potential of the bit line with a decision threshold and outputs a comparison result by an output circuit, and sets the potential at the decision point at a time of precharging in correspondence with the decision threshold. A capacitor element connects between the bit line and an input end of the output circuit. A potential setting circuit enables setting of an input end of the output circuit forming a decision point, to a prescribed potential between a precharge voltage of the bit line and the decision threshold at a time of precharging the bit line. Operating range of memory function is enlarged.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: March 4, 2014
    Assignee: Elpida Memory, Inc.
    Inventor: Shin Ito
  • SEMICONDUCTOR DEVICE HAVING CURRENT CHANGE MEMORY CELL
    Publication number: 20140056063
    Abstract: A method includes performing a read operation on a memory cell of a device including a sensing line, a bit line coupled to the memory cell, a first transistor having a source-drain path coupled between the sensing line and the bit line, and a second transistor having a gate coupled to sense the sensing line, the performing including providing a gate of the first transistor with a first voltage, providing the sensing line with a second voltage, and providing the bit line with a third voltage, the third voltage being independent from the second voltage.
    Type: Application
    Filed: October 28, 2013
    Publication date: February 27, 2014
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kazuhiko Kajigaya
  • SEMICONDUCTOR MEMORY DEVICE, METHOD OF ADJUSTING THE SAME AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME
    Publication number: 20140056086
    Abstract: A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.
    Type: Application
    Filed: November 1, 2013
    Publication date: February 27, 2014
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hideyuki Yoko, Naohisa Nishioka, Chikara Kondo, Ryuji Takishita
  • SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR PILLAR
    Publication number: 20140048860
    Abstract: Disclosed herein is a device that includes: first to fourth conductive lines embedded in a semiconductor substrate; a first semiconductor pillar located between the first and second conductive lines; a second semiconductor pillar located between the second and third conductive lines; a third semiconductor pillar located between the third and fourth conductive lines; a first storage element connected to an upper portion of the first semiconductor pillar; a second storage element connected to an upper portion of the third semiconductor pillar; and a bit line embedded in the semiconductor substrate connected to lower portions of the first to third semiconductor pillars. At least one of the first and second conductive lines and at least one of the third and fourth conductive lines being supplied with a potential so as to form channels in the first and third semiconductor pillars.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 20, 2014
    Applicant: Elpida Memory, Inc.
    Inventors: Noriaki MIKASA, Yoshihiro TAKAISHI
  • SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES
    Publication number: 20140050004
    Abstract: Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 20, 2014
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Noriaki MOCHIDA
  • Semiconductor device generates complementary output signals
    Patent number: 8653874
    Abstract: A splitter circuit in a semiconductor device includes a first inverter that receives an input signal and outputs an inverted signal, a second inverter that receives the inverted signal and outputs a non-inverted signal (a first output signal), a third inverter that receives the input signal and outputs an inverted signal (a second output signal) and an auxiliary inverter that shares an output signal line with the third inverter. The third inverter and the auxiliary inverter use an inverted signal of the input signal as power supplies.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: February 18, 2014
    Assignee: Elpida Memory, Inc.
    Inventors: Takenori Sato, Shinya Miyazaki
  • SEMICONDUCTOR DEVICE
    Publication number: 20140042589
    Abstract: The semiconductor device 200 includes a wiring substrate 201, a lower chip 203 mounted on a surface of the wiring substrate 201, and an upper chip 205 mounted on the lower chip 203, the lower chip 203 includes a plurality of fuse opening portions 113, each of the fuse opening portions 113 is fully covered with or fully exposed from the upper chip 205.
    Type: Application
    Filed: January 23, 2013
    Publication date: February 13, 2014
    Applicant: Elpida Memory, Inc.
    Inventor: Jun FUJII
  • SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR PILLAR
    Publication number: 20140042555
    Abstract: Disclosed herein is a device that includes: a semiconductor substrate including an active region having a semiconductor pillar, the semiconductor pillar having first and second side surfaces substantially perpendicular to a main surface of the semiconductor substrate; an element isolation region surrounding the active region, the element isolation region including a first insulating pillar that is in contact with the first side surface of the semiconductor pillar; a gate electrode that covers the second side surface of the semiconductor pillar with an intervention of a gate insulating film; a first impurity diffusion layer formed on an upper surface of the semiconductor pillar; a second impurity diffusion layer formed in the active region located below the semiconductor pillar; and an etching protection wall that is arranged to surround the semiconductor pillar.
    Type: Application
    Filed: July 26, 2013
    Publication date: February 13, 2014
    Applicant: Elpida Memory, Inc.
    Inventor: Yoshihiro TAKAISHI
  • SEMICONDUCTOR DEVICE
    Publication number: 20140043885
    Abstract: In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other.
    Type: Application
    Filed: October 15, 2013
    Publication date: February 13, 2014
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Yoshiro RIHO
  • SEMICONDUCTOR DEVICE HAVING PENETRATION ELECTRODE
    Publication number: 20140042617
    Abstract: Disclosed herein is a semiconductor device that includes: a semiconductor substrate including first and second surfaces opposed to each other, a plurality of penetration electrodes each penetrating between the first and second surfaces and a plurality of first metal films each surrounding an associated one of the penetration electrodes with an intervention of an insulating film; and a wiring structure formed on a side of the first surface of the semiconductor substrate, the wiring structure including a plurality of wirings each electrically connected to an associated one of the penetration electrodes.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 13, 2014
    Applicant: Elpida Memory, Inc.
    Inventor: Shirou UCHIYAMA
  • Anneal to minimize leakage current in DRAM capacitor
    Patent number: 8647960
    Abstract: A method for forming a DRAM MIM capacitor stack comprises forming a first electrode layer, annealing the first electrode layer, forming a dielectric layer on the first electrode layer, annealing the dielectric layer, forming a second electrode layer on the dielectric layer, annealing the second electrode layer, patterning the capacitor stack, and annealing the capacitor stack for times greater than about 10 minutes, and advantageously greater than about 1 hour, at low temperatures (less than about 300 C) in an atmosphere containing less than about 25% oxygen and preferably less than about 10% oxygen.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: February 11, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Wim Deweerd, Hiroyuki Ode
  • Enhanced non-noble electrode layers for DRAM capacitor cell
    Patent number: 8647943
    Abstract: A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode materials are conductive molybdenum oxide.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 11, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Hanhong Chen, Wim Y. Deweerd, Edward L Haywood, Sandra G Malhotra, Hiroyuki Ode
  • Semiconductor device and method of manufacturing the same
    Patent number: 8648455
    Abstract: A semiconductor device includes a wiring substrate having an insulating film formed on a surface thereof, a first semiconductor chip mounted on the wiring substrate, and a second semiconductor chip stacked and mounted on the first semiconductor chip so as to form an overhang portion. The insulating film is removed from an area of the wiring substrate that faces the overhang portion.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: February 11, 2014
    Assignee: Elpida Memory, Inc.
    Inventor: Hidehiro Takeshima
  • Semiconductor device including first semiconductor chip including first pads connected to first terminals, and second semiconductor chip including second pads connected to second terminals
    Patent number: 8648339
    Abstract: A semiconductor device includes a plurality of first data input/output terminals, a plurality of second data input/output terminals, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a plurality of first data input/output pads connected with the first data input/output terminals, a first test circuit, and a first memory portion. The first test circuit generates a first test result in response to a data output from the first memory portion at a test operation. The second semiconductor chip includes a plurality of second data input/output pads connected with the second data input/output terminals, a second and a third test circuits, and a second memory portion.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: February 11, 2014
    Assignee: Elpida Memory, Inc.
    Inventors: Takahiro Koyama, Sadayuki Okuma
  • Circuit including first and second transistors coupled between an outpout terminal and a power supply
    Patent number: 8648585
    Abstract: A constant current source circuit is constituted of a control voltage generation section which detects the output voltage at the output terminal so as to generate a control voltage, a reference current adjustment section which adjust a reference current based on the control voltage, and a current mirror section which outputs the output current responsive to the adjusted reference current at the output terminal. This reduces variations of the output current due to variations of the output voltage; hence, the constant current source circuit can precisely operate in a low-voltage region.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: February 11, 2014
    Assignee: Elpida Memory, Inc.
    Inventor: Akira Ide