Abstract: Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The arrangement includes a first bonding finger array, which is located at a close distance from each longer side of the slot, and a second array, which is located at a farther distance than the distance of the first bonding finger array from each longer side of the slot. The central section of the bonding finger area includes the second bonding finger array, and the end sections of the bonding finger area include the first bonding finger array.

Abstract: A semiconductor chip 109 is mounted on a substrate 100, first wire group 120 and a second wire group 118 having a wire length shorter than the first wire group are provided so as to connect the substrate 100 and the semiconductor chip 109 to each other, and a sealing resin 307 is injected from the first wire group 120 toward the second wire group 118 so as to form a sealer 401 covering the semiconductor chip 109, the first wire group 120, and the second wire group 118.

Abstract: A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells. A first transistor is between the output node of the first amplifier and a first data line and is turned ON in response to a first selection signal to convey the first data signal from the first amplifier onto the first data line. A second amplifier is coupled to the first data line and amplifies, when activated, the first data signal, and is further coupled to the first signal line and activated in response to a first activation signal that is transferred through a first signal line. A second transistor is coupled to the first signal line and is turned ON in response to the first selection signal to the first signal line.

Abstract: A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.

Abstract: A plurality of memory cells are tested in order. Each time a defective memory cell is detected by the test, error pattern information is updated based on a relative arrangement relationship between a plurality of defective memory cells, and error address information is updated based on the addresses of at least part of the plurality of defective memory cells. According to the present invention, it is possible to significantly reduce the storage capacity of the analysis memory. This allows the implementation of the analysis memory itself in the semiconductor device, in which case external testers need not include the analysis memory.

Abstract: A semiconductor device according to the present invention includes plural core chips CC0 to CC7 to which mutually different pieces of chip identification information LID are allocated, and an interface chip IF that controls the core chips CC0 to CC7. The interface chip IF receives address information ADD for specifying a memory cell, and supplies in common a part of the address information to the core chips CC0 to CC7 as chip selection information SEL to be compared with the chip identification information LID. With this configuration, it appears from a controller that an address space is simply enlarged. Therefore, an interface that is same as that for a conventional semiconductor memory device can be used.

Abstract: A method includes accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line; transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and restoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line.

Abstract: A control circuit controls memory operations such that, in a first rewriting operation in which a resistance state of a variable resistance element is changed from a first state to a second state, a first voltage pulse is applied to both terminals of a memory cell while limiting the amount of current flowing through the variable resistance element to a value smaller than or equal to a certain small amount of current, in a second rewriting operation in which the resistance state of the variable resistance element is changed from the second state to the first state, a second voltage pulse is applied to both terminals of the memory cell, and, in a reading operation in which the resistance state stored in the variable resistance element is read, a third voltage pulse is applied to both terminals of the memory cell.

Abstract: The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side.

Abstract: A method of manufacturing a semiconductor device includes: supplying a supercritical fluid mixed with an under-fill material to a stacked unit, which has a plurality of stacked semiconductor chips; and filling the under-fill material in the space between the plurality of the semiconductor chips, by heating the stacked unit placed in the inside of the high-pressure vessel and curing the under-fill material flowing in the space between the plurality of the semiconductor chips by a polymerization reaction, while the supercritical fluid is being supplied.

Abstract: Such a device is disclosed that includes a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals, and a second semiconductor chip including a plurality of third terminals coupled respectively to the second terminals, an internal circuit, and a second circuit coupled between the third terminals and the internal circuit and configured to activate the internal circuit when a combination of signals appearing at the third terminals indicates a chip selection.

Abstract: To include a refresh control circuit that generates a refresh execution signal in response to a refresh command supplied from outside, and a refresh address counter that performs a counting operation in response to activation of the refresh execution signal. The refresh control circuit generates the refresh execution signal 2n times in response to one supply of the refresh command, where n is an integer equal to or larger than 0 and equal to or less than k. The value of n is variable based on a refresh-mode specifying signal supplied from outside in synchronization with the refresh command. With this configuration, for example, a frequency of generation of the refresh execution signal in response to one supply of the refresh command can be changed dynamically, flexible control can be performed by a controller.

Abstract: A device includes first and second regions including first and second amplifiers, respectively and a memory cell array region formed between the first and second regions and includes first and second conductive layers each extending in a first direction, and a plurality of first pillar elements arranged in line in the first direction on the first conductive layer, each of the first pillar elements being coupled to the first conductive layer at one end thereof, and the first pillar elements comprising a plurality of first elements and a second element, and a plurality of second pillar elements arranged in line in the first direction on the second conductive layer, each of the second pillar elements being coupled to the second conductive layer at one end thereof, and the second pillar elements comprising a plurality of third elements and a fourth element.

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers.

Abstract: For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract: A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data.

Abstract: A system includes a first device, a second device, and a bus interconnecting the first and second devices to each other, wherein the first device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a first data electrode, and a first data control circuit coupled to the first control logic circuit and the first data electrode.

Abstract: A semiconductor device is disclosed, which comprises first and second input ports, first and second output nodes, and first and second transistors. The first transistor includes first and second diffusion regions defining a first channel region and a first gate electrode and connected to the first input port, the first diffusion region being connected to the first output node, the second diffusion region being disposed between the first diffusion region and the first input port and supplied with a first operating potential. The second transistor includes third and fourth diffusion regions defining a second channel region and a second gate electrode and connected to the second input port, the third diffusion region being supplied with the first operating potential, the fourth diffusion region being disposed between the third diffusion region and the second input port and connected to the second output node.

Abstract: A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks.