Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract: A device includes first and second regions including first and second amplifiers, respectively and a memory cell array region formed between the first and second regions and includes first and second conductive layers each extending in a first direction, and a plurality of first pillar elements arranged in line in the first direction on the first conductive layer, each of the first pillar elements being coupled to the first conductive layer at one end thereof, and the first pillar elements comprising a plurality of first elements and a second element, and a plurality of second pillar elements arranged in line in the first direction on the second conductive layer, each of the second pillar elements being coupled to the second conductive layer at one end thereof, and the second pillar elements comprising a plurality of third elements and a fourth element.

Abstract: For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.

Abstract: A semiconductor device is disclosed, which comprises first and second input ports, first and second output nodes, and first and second transistors. The first transistor includes first and second diffusion regions defining a first channel region and a first gate electrode and connected to the first input port, the first diffusion region being connected to the first output node, the second diffusion region being disposed between the first diffusion region and the first input port and supplied with a first operating potential. The second transistor includes third and fourth diffusion regions defining a second channel region and a second gate electrode and connected to the second input port, the third diffusion region being supplied with the first operating potential, the fourth diffusion region being disposed between the third diffusion region and the second input port and connected to the second output node.

Abstract: A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks.

Abstract: A system includes a first device, a second device, and a bus interconnecting the first and second devices to each other, wherein the first device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a first data electrode, and a first data control circuit coupled to the first control logic circuit and the first data electrode.

Abstract: A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure.

Abstract: A system includes a first circuit, a second circuit including a logic circuit, and a bus interconnecting the first and second circuits to each other so that the second circuit accesses the first circuit to perform a data transfer therebetween, wherein the first circuit includes a first sense amplifier array including a plurality of first sense amplifiers that are arranged in a first direction, each of the first sense amplifiers including first and second nodes; and a plurality of first global bit lines each extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that each of the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers.

Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.

Abstract: A memory cell changes a potential of a bit line to a discharge potential from a precharge potential in correspondence with held data. A sense amplifier precharges a bit line by a precharge circuit, compares potential at a decision point linked with the potential of the bit line with a decision threshold and outputs a comparison result by an output circuit, and sets the potential at the decision point at a time of precharging in correspondence with the decision threshold. A capacitor element connects between the bit line and an input end of the output circuit. A potential setting circuit enables setting of an input end of the output circuit forming a decision point, to a prescribed potential between a precharge voltage of the bit line and the decision threshold at a time of precharging the bit line. Operating range of memory function is enlarged.

Abstract: Disclosed herein is a device that includes: first to fourth conductive lines embedded in a semiconductor substrate; a first semiconductor pillar located between the first and second conductive lines; a second semiconductor pillar located between the second and third conductive lines; a third semiconductor pillar located between the third and fourth conductive lines; a first storage element connected to an upper portion of the first semiconductor pillar; a second storage element connected to an upper portion of the third semiconductor pillar; and a bit line embedded in the semiconductor substrate connected to lower portions of the first to third semiconductor pillars. At least one of the first and second conductive lines and at least one of the third and fourth conductive lines being supplied with a potential so as to form channels in the first and third semiconductor pillars.

Abstract: A splitter circuit in a semiconductor device includes a first inverter that receives an input signal and outputs an inverted signal, a second inverter that receives the inverted signal and outputs a non-inverted signal (a first output signal), a third inverter that receives the input signal and outputs an inverted signal (a second output signal) and an auxiliary inverter that shares an output signal line with the third inverter. The third inverter and the auxiliary inverter use an inverted signal of the input signal as power supplies.

Abstract: Disclosed herein is a device that includes: a semiconductor substrate including an active region having a semiconductor pillar, the semiconductor pillar having first and second side surfaces substantially perpendicular to a main surface of the semiconductor substrate; an element isolation region surrounding the active region, the element isolation region including a first insulating pillar that is in contact with the first side surface of the semiconductor pillar; a gate electrode that covers the second side surface of the semiconductor pillar with an intervention of a gate insulating film; a first impurity diffusion layer formed on an upper surface of the semiconductor pillar; a second impurity diffusion layer formed in the active region located below the semiconductor pillar; and an etching protection wall that is arranged to surround the semiconductor pillar.

Abstract: Disclosed herein is a semiconductor device that includes: a semiconductor substrate including first and second surfaces opposed to each other, a plurality of penetration electrodes each penetrating between the first and second surfaces and a plurality of first metal films each surrounding an associated one of the penetration electrodes with an intervention of an insulating film; and a wiring structure formed on a side of the first surface of the semiconductor substrate, the wiring structure including a plurality of wirings each electrically connected to an associated one of the penetration electrodes.

Abstract: The semiconductor device 200 includes a wiring substrate 201, a lower chip 203 mounted on a surface of the wiring substrate 201, and an upper chip 205 mounted on the lower chip 203, the lower chip 203 includes a plurality of fuse opening portions 113, each of the fuse opening portions 113 is fully covered with or fully exposed from the upper chip 205.

Abstract: A semiconductor device includes a wiring substrate having an insulating film formed on a surface thereof, a first semiconductor chip mounted on the wiring substrate, and a second semiconductor chip stacked and mounted on the first semiconductor chip so as to form an overhang portion. The insulating film is removed from an area of the wiring substrate that faces the overhang portion.

Abstract: A constant current source circuit is constituted of a control voltage generation section which detects the output voltage at the output terminal so as to generate a control voltage, a reference current adjustment section which adjust a reference current based on the control voltage, and a current mirror section which outputs the output current responsive to the adjusted reference current at the output terminal. This reduces variations of the output current due to variations of the output voltage; hence, the constant current source circuit can precisely operate in a low-voltage region.

Abstract: A semiconductor device includes a plurality of first data input/output terminals, a plurality of second data input/output terminals, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a plurality of first data input/output pads connected with the first data input/output terminals, a first test circuit, and a first memory portion. The first test circuit generates a first test result in response to a data output from the first memory portion at a test operation. The second semiconductor chip includes a plurality of second data input/output pads connected with the second data input/output terminals, a second and a third test circuits, and a second memory portion.

Abstract: A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode materials are conductive molybdenum oxide.