Abstract: A floating-point value can represent a number or something that is not a number (NaN). A floating-point value that is a NaN includes a portion that stores information about the source operands of the instruction.

Abstract: A system method of initializing operation of a semiconductor device including detecting de-assertion of an external reset signal while the semiconductor device in a reset state, monitoring a temperature level of the semiconductor device, and while the temperature level is below a predetermined minimum operating temperature level that allows the semiconductor device to operate at a maximum performance level, keeping the semiconductor device in the reset state and asserting at least one operating parameter on the semiconductor device at an elevated level to generate heat on the semiconductor device, and releasing the reset condition when the temperature level is at least the predetermined minimum operating temperature level. The operating parameter may be clock frequency or supply voltage level or a combination of both. Different elevated clock frequencies and/or different minimum operating temperature levels are contemplated.

Abstract: A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.

Abstract: A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal pillars. The first die and the second die are stacked such that each metal pillar extends from a surface of the second die to a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal pillars and the corresponding pads.

Abstract: An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal.

Abstract: A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby c

Abstract: A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure.

Abstract: An integrated circuit includes first and second memory cells including a first pull-up transistor each having a body tie coupled to respective first and second well bias voltages. Drain electrodes of the first and second pull-up transistors are coupled to a first true bit line and a first complementary bit line, respectively. A second memory cell includes first and second pull-up transistors each having a body tie coupled to the second and first well bias voltages, respectively. Drain electrodes of the first and second pull-up transistors are coupled to a second true bit line and a second complementary bit line, respectively. The first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.

Abstract: An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.

Abstract: A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.

Abstract: A battery charging circuit comprises: a first voltage regulator, wherein the first voltage regulator has a control input designed for reception of a signal generated by a current metering circuit; the current metering circuit; and a terminal for connecting a battery. An electronic device, in particular a mobile device, comprises a battery charging circuit as defined above.

Abstract: A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.

Abstract: An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate. The first electrostatic discharge protection device includes a buried layer formed over the substrate, the buried layer having a first conductivity type and defining an opening located over a region of the substrate, a first transistor formed over the opening of the buried layer, the first transistor having an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp, and a second transistor formed over the buried layer, the second transistor having an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp.

Abstract: Etch stabilizing ions (37) are introduced, e.g., by ion implantation (34), into a portion (36) of a substrate (20) underlying an etch window (24) in a masking layer (22) covering the substrate (20), where a trench (26) is desired to be formed. When the portion (36) of the substrate (20) containing the etch stabilizing ions (37) is etched to form the trench (26), the etch stabilizing ions (37) are progressively released at the etch interface (28?) as etching proceeds, substantially preventing gas micro-bubbles or other reaction products at the etch interface (28?) from disrupting etching. Using this method (700), products containing trenches (26) are much more easily formed and such trenches (26) have much smoother interior surface (28).

Abstract: A push-push oscillator circuit with a first oscillation branch with a first active device and a first tank adapted to provide a signal having a fundamental frequency f0, a second oscillation branch with a second active device and a second tank symmetrical to the first oscillation branch and adapted to provide a signal having the fundamental frequency f0. Output branches are coupled to the first oscillation branch and the second oscillation branch to provide signals having the second harmonic frequency 2f0 of the fundamental signal based on the signals having the fundamental frequency f0 and/or to provide signals having the fundamental frequency f0; The push-push oscillator circuit further comprises at least one terminal branch with a terminal adapted to provide a component of a differential signal having the second harmonic frequency 2f0 or the fundamental frequency f0. The at least one terminal branch comprises a RF stub.

Abstract: A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

Abstract: A semiconductor device is formed such that a semiconductor substrate of the device has a non-uniform thickness. A cavity is etched at a selected side of the semiconductor substrate, and the selected side is then fusion bonded to another substrate, such as a carrier substrate. After fusion bonding, the side of the semiconductor substrate opposite the selected side is ground to a defined thickness. Accordingly, the semiconductor substrate has a uniform thickness except in the area of the cavity, where the substrate is thinner. Devices that benefit from a thinner substrate, such as an accelerometer, can be formed over the cavity.

Abstract: Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and where the voltage has a value outside of a voltage supply range of the logic circuit. In another embodiment, a semiconductor device may include a biasing circuit configured to generate a voltage that varies according to a temperature of the semiconductor device and a power switch operably coupled to the biasing circuit, where the voltage is applied to a gate terminal of the power switch, and where the voltage has a value outside of a voltage supply range of the power switch.

Abstract: An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. The device further comprises a second power switch connectable or connected between a second voltage source and the load. The second power switch assumes a conductive state in response to the power-on request and a non-conductive state when the voltage across the first power switch is below a defined switch-off threshold lower than the high level. The second voltage source thus assists the first voltage source in powering up the load.

Abstract: A heating system is described for generating heat and bringing heat to a semiconductor device under test. The heating system comprises a conduction heating unit comprising a heating resistor, a thermal contact area for thermally contacting the semiconductor device under test, and a thermally conductive and electrically insulating connection between the heating resistor and the thermal contact area. The heating resistor is operable to generate a user-defined amount of heat and arranged to provide a part of the heat generated by the heating resistor to the thermal contact area via the thermally conductive and electrically insulating connection. It is also described that the heating system may further comprise a convection heating chamber operable to provide a user-defined heat-controlled convection to the semiconductor device under test. A method of testing a semiconductor device using a heating system is also described.