Abstract: An integrated circuit device comprising at least one calibration module for calibrating an impedance of at least one on-die interconnect line driver in order to adaptively match an impedance between the at least one on-die interconnect line driver and at least one on-die interconnect line conjugated thereto. The at least one calibration module is arranged to receive an indication of an output signal of the at least one line driver, compare the received indication of an output signal to a reference signal and detect a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, and upon detection of a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, cause the adjustment of power supply of the at least one line driver, to be decreased or increased correspondingly.

Abstract: A diversity receiver comprises a plurality of receiving paths connected to a receiver circuit. Each of the receiving paths comprises an antenna receiving a signal, connected to a matching network connected to a receive amplifier. The receiver circuit is connected to a signal level comparison circuit for providing a relative comparison value indicating one of the receiving paths receiving the signal with a relative maximum strength. The signal level comparison circuit comprises a comparator circuit connected to the receiver circuit receiving a currently received signal level, and to a logic control unit being arranged to select one of the receive paths to provide the currently received signal to the receiver circuit.

Abstract: An electronic design automation (EDA) tool for inserting dummy tiles between interconnect lines of an integrated circuit design includes a memory for storing the integrated circuit design and a processor in communication with the memory. The processor identifies those interconnect lines that are at different voltage levels, have a length greater than a predefined threshold length and a spacing less than a predefined threshold spacing, and inserts blockage areas between such interconnect lines. The processor skips the blockage areas and adds dummy tiles only between those interconnect lines that do not meet predetermined criteria.

Abstract: A method includes preferentially placing fill regions adjacent to transistors of a particular conductivity type, such as p-channel transistors, for a plurality of standard cell instances of a device design. The method also includes evaluating all transistors of the first conductivity type prior to evaluating any transistors of a second conductivity type. The second conductivity type is opposite the first conductivity type. For each transistor being evaluated, it is determined whether a criterion is me. A fill region is placed within a field isolation region adjacent to the transistor if the criterion is met.

Abstract: A device for forming a high-resolution image of an object is provided. The device comprises: an electronic camera for capturing an intermediate image of the object, an illumination system for forming a spatial modulation pattern on the object; and a spatial demodulator for performing a spatial demodulation, which is at least partially matched to the spatial modulation pattern. A method for deriving a high-spatial-resolution image from a set of images captured from a structure of an object is derived, wherein the illumination of the object is spatially-modulated, wherein the illumination of the object has a spatial modulation pattern, which is substantially periodic, wherein one of at least one prevailing orientation of the periodic illumination is arranged substantially perpendicularly to at least one prevailing orientation of the structure of the object.

Abstract: A capacitance sensing circuit comprises a capacitive device having a capacitance, the device initially being at a first voltage level. The capacitance sensing circuit is capable of applying one or more pull-up currents to the device during one or more corresponding pull-up periods of time, for changing the first voltage level into one or more corresponding pull-up voltage levels; applying a measurement current to the device; and measuring a measurement period of time, during which one of the pull-up voltage levels changes into a second voltage level. A method of sensing a capacitance of a capacitive device comprises applying a first voltage to the device; applying one or more pull-up currents during corresponding pull-up times, for changing the first voltage into corresponding pull-up voltages; applying a measurement current; and measuring a time, during which one pull-up voltage changes into a second voltage.

Abstract: A non-volatile memory device comprises an array of memory cells and a charge pump coupled to the memory cells. The charge pump is dynamically reconfigurable to operate in a bypass mode to provide a first voltage to the memory cells, a program mode to provide the first voltage to the memory cells, and an erase mode to provide a second voltage that has inverse polarity of the first voltage.

Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

Abstract: An assembly (20) includes a MEMS die (22) having a pressure transducer device (40) formed on a substrate (44) and a cap layer (38). A packaging process (74) entails forming the device (40) on the substrate, creating an aperture (70) through a back side (58) of the substrate underlying a diaphragm (46) of the device (40), and coupling a cap layer (38) to the front side of the substrate overlying the device. A trench (54) is produced extending through both the cap layer and the substrate, and the trench surrounds a cantilevered platform (48) at which the diaphragm resides. The MEMS die is suspended above a substrate (26) so that a clearance space (60) is formed between the cantilevered platform and the substrate. The diaphragm is exposed to an external environment (68) via the aperture, the clearance space, and an external port.

Abstract: A gateway includes a network interface and an apparatus for detecting predetermined tones The apparatus includes an input to receive a signal transmitted over the network interface, a frequency divider to divide the signal into two different components, each component being associated with a different frequency sub band, wherein each frequency sub band is selected to include a predetermined frequency of a predetermined tone, a frequency discriminator to determine frequencies of tones in the components, and a decision logic block to provide an indication that a first predetermined tone has been detected when a first determined frequency of a first tone in a first component corresponds to a first predetermined frequency of the first tone.

Abstract: A power supply that provides a supply voltage to an integrated circuit (IC) includes high and low power regulators and a power management circuit. The high power regulator regulates the supply voltage at a first voltage level and the low power regulator is set to an inactive mode when the IC is in a RUN mode. When the IC transitions from the RUN mode to a STOP mode, the high power regulator stops regulating and the supply voltage is maintained at a second voltage level, while the lower power regulator is set to an active mode for regulating the supply voltage at a third voltage level. A fallback signal is generated when the supply voltage drops below a first threshold value after which the low power regulator is set in the inactive mode and the high power regulator is configured to regulate the supply voltage at a fourth voltage level.

Abstract: A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A conductive material fills the opening. The opening has a length direction and a width direction and a first and second feature. The first feature and the second feature are spaced apart by a first length. The first feature has first width as a maximum width of the first feature, and the second feature has a second width as the maximum width of the second feature. The opening has a minimum width between the first feature and the second feature that is no more than one fifth the first length. The first width and the second width are each at least twice the minimum width.

Abstract: An assembly (20) includes a MEMS die (22) having a pressure transducer device (40) formed on a substrate (44) and a cap layer (38). A packaging process (74) entails forming the device (40) on the substrate, creating an aperture (70) through a back side (58) of the substrate (44) underlying a diaphragm (46) of the device (40), and coupling a cap layer (38) to the front side of the substrate (44) overlying the device (40). A trench (54) is produced extending through both the cap layer (38) and the substrate (44), and surrounds a cantilevered platform (48) at which the diaphragm (46) resides. The die (22) is suspended above a substrate (26) so that a clearance space (60) is formed between the platform (48) and the substrate (26). The diaphragm (46) is exposed to an external environment (68) via the aperture (70) and the space (60), and an external port.

Abstract: A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.

Abstract: A bond pad region is provided that reduces parasitic capacitance generated between bond pad metallization and underlying silicon by reducing the effective area of the bond pad, while maintaining flexibility of wire bond sites and ensuring mechanical integrity of the wire bonds. Embodiments provide, in a region that would be populated by a traditional bus bar bond pad, a small bus bar bond pad that is less than half the area of the region and populating at least a portion of the remaining area with metal tiles that are not electrically connected to the small bus bar bond pad or to each other. The metal tiles provide an attachment area for at least a portion of one or more wire bonds. Only those tiles involved in connection to a wire bond contribute to parasitic capacitance, along with the small bus bar pad.

Abstract: A system for synchronizing a functional reset between first and second clock domains that operate on first and second clock signals, respectively. The system includes first, second and third synchronizer flip-flops that operate on the second clock signal. The first synchronizer flip-flop receives a functional reset signal generated by the first clock domain at its reset terminal and generates a low output signal. The low output signal causes the second synchronizer flip-flop and subsequently the third synchronizer flip-flop to generate low output signals at positive edges of the second clock signal. The low output signal generated by the third synchronizer flip-flop is used to reset the second clock domain.

Abstract: An integrated circuit package includes an electronic sensor protected by a lid structure. The electronic sensor includes a transducer placed on a backside surface of a lead frame assembly. The lid structure is placed over the transducer and is attached to the lead frame assembly on the backside surface. The lid can define an air cavity around the transducer, such that mold compound, gel, or other protective chemical material is not placed in contact with the transducer. The transducer is therefore protected without a chemical protectant, lowering the cost of the integrated circuit package and maintaining the sensitivity and performance of the transducer.

Abstract: A voltage switching circuitry comprises a switching arrangement with a given number N of switches in series between a first terminal receiving a first voltage and a second terminal receiving a second voltage. The first voltage level is higher than the second voltage level, and N is at least equal to 2. A voltage-by-N divider, having N?1 output taps, is arranged to divide the first voltage by N to a scaled down version of the first voltage having a voltage level below voltage max ratings of the switches. The N?1 output taps of the divider are arranged to respectively output N?1 third voltages having respective levels staged below the first voltage level. N?1 max voltage generators generate N?1 fourth voltages, respectively equal to the maximum of the second voltage and of each of the N?1 third voltages. A switch control unit generates N control signals using the N?1 fourth voltages. These N control signals have respective voltage levels staged between the first voltage level and the second voltage level.

Abstract: A transconductance amplification stage (301) includes a differential pair (306) wherein a bias current flows through each transistor (302, 304) of the pair when input voltages are equal. Tail current boosting circuitry (320), which includes a tail transistor, provides a translinear expansion of tail current of the differential pair. A feedback loop (307) dynamically biases the differential pair to maintain current through one transistor (302) of the pair at the bias current value in spite of a difference between input voltages. Another transistor (304) of the pair provides an output current responsive to a difference between input voltages. The output current is not affected by a region of operation of the tail transistor. An output structure (300, 500) includes the transconductance amplification stage and a circuit (303) for mirroring the output current. An amplifier (800) includes the output structure as a buffer between other structures (801) and an output terminal.

Abstract: An on-die capacitance measurement module (ODCMM) arranged to measure a capacitance element. The ODCMM comprises an oscillating voltage supply that outputs first and second oscillating voltage signals, the first and second oscillating voltage signals comprising differing phases, and the oscillating voltage supply component coupled to a first node of the capacitance element and arranged to provide thereto the first oscillating voltage signal, and a reference voltage component coupled to a second node of the capacitance element to provide a reference voltage signal. The ODCMM operates in a first mode, wherein the reference voltage component is arranged to provide a constant reference voltage to the second node of the capacitance element.