Patents Assigned to Freescale
  • PROCESSING LOAD WITH NORMAL OR FAST OPERATION MODE
    Publication number: 20140337859
    Abstract: A data processing apparatus includes a processing unit having first and second modes of operation for processing data, including receiving data packets from a sender and sending acknowledgements to the sender, the second mode of operation requires more power than the first mode, and the processing unit switches between the first and second modes of operation based on a processing load; a metric module for determining a metric indicative of the processing load; an acknowledgement module for sending one acknowledgement in respect of n received data packets; and an acknowledgement configuration module for setting n to be a value m greater than a first predetermined value if the metric lies in a predetermined range that includes a value that the metric assumes when the processing unit switches between the first mode of operation and the second mode of operation, and to the first predetermined value otherwise.
    Type: Application
    Filed: July 25, 2014
    Publication date: November 13, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: JEAN-LUC ROBIN
  • SEMICONDUCTOR DEVICE WITH NOTCHED GATE
    Publication number: 20140332901
    Abstract: A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, a drain region disposed in the semiconductor substrate, having the second conductivity type, and spaced from the source region to define a conduction path, a gate structure supported by the semiconductor substrate, configured to control formation of a channel in the conduction path during operation, and having a side adjacent the source region that comprises a notch, the notch defining a notch area, and a notch region disposed in the semiconductor substrate in the notch area and having the first conductivity type.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 13, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Pete Rodriquez, Zhihong Zhong, Jiang-Kai Zuo
  • METAL-OXIDE-SEMICONDUCTOR (MOS) VOLTAGE DIVIDER WITH DYNAMIC IMPEDANCE CONTROL
    Publication number: 20140333367
    Abstract: Metal-Oxide-Semiconductor (MOS) voltage divider with dynamic impedance control. In some embodiments, a voltage divider may include two or more voltage division cells, each voltage division cell having a plurality of Metal-Oxide-Semiconductor (MOS) transistors, a least one of the plurality of MOS transistors connected to a signal path and at least another one of the plurality of MOS transistors connected to a control path, the voltage division cell configured to provide a voltage drop across the signal path based upon a control signal applied to the control path.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 13, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Ricardo P. Coimbra, Edevaldo Pereira Silva, JR.
  • OVER-CURRENT PROTECTION DEVICE
    Publication number: 20140334053
    Abstract: An over-current protection circuit including, a current supply switch with a first terminal coupled to a supply current input and with a second terminal coupled to a supply current output. The current supply switch is switchable at least between an on-state, in which the current supply switch provides a conductive connection between the first terminal and the second terminal, and an off-state, in which the current supply switch interrupts the conductive connection between the first terminal and the second terminal. The over-current protection circuit receives a supply current via the supply current input and provides the supply current via the supply current output if the switch is in the on-state. The current supply switch includes High Electron Mobility Transistor.
    Type: Application
    Filed: January 20, 2012
    Publication date: November 13, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Philippe Renaud, Philippe Dupuy
  • SYSTEM, METHOD AND APPARATUS FOR LEADLESS SURFACE MOUNTED SEMICONDUCTOR PACKAGE
    Publication number: 20140332941
    Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.
    Type: Application
    Filed: July 25, 2014
    Publication date: November 13, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lakshminarayan Viswanathan, Lakshmi N. Ramanathan, Audel A. Sanchez, Fernando A. Santos
  • Processor switchable between test and debug modes
    Patent number: 8887017
    Abstract: A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Akshay K. Pathak, Rakesh Pandey
  • Electronic device with power mode control buffers
    Patent number: 8884669
    Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiaoxiang Geng, Zhihong Cheng, Huabin Du, Miaolin Tan
  • Programming a split gate bit cell
    Patent number: 8885403
    Abstract: A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong M. Hong, Ronald J. Syzdek, Brian A. Winstead
  • Timing path slack monitoring system
    Patent number: 8887120
    Abstract: An on-chip timing slack monitor that measures timing slack at the end of a critical path includes a master-slave flip-flop having a tap on the Q output of the master and a logic module coupled to the flip-flop for producing a pulse whose width is a function of the slack. A pulse width shrinking delay line removes glitches on the flip-flop output and, in combination with a digital integrator and counter, also performs a time to digital conversion operation for determining a value for timing path slack. The determined value is used by a decision module for yield analysis. The monitor can discriminate a glitch from a slack pulse at the flip-flop output for any width of glitch up to one-half of a clock cycle.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chetan Verma, Amit Kumar Dey, Amit Roy, Vijay Tayal
  • Method of making a non-volatile memory (NVM) cell structure
    Patent number: 8884358
    Abstract: A non-volatile memory device includes a substrate and a charge storage layer. The charge storage layer comprises a bottom layer of oxide, a layer of discrete charge storage elements on the bottom layer of oxide, and a top layer of oxide on the charge storage elements. A control gate is on the top layer of oxide. A surface of the top layer of oxide facing a surface of the control gate is substantially planar.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Sung-Taeg Kang, Marc A. Rossow
  • System and method for low-latency addressing in flash memory
    Patent number: 8886874
    Abstract: A system for operating a flash memory includes a memory controller in communication with a processor. The memory controller includes a memory read access command receiver that receives a memory read access command from the processor. The memory read access command includes a memory cell address of a memory cell to be accessed for the execution of the memory read accessed command. The memory cell address includes a current sector address and a sector specific memory cell address. The flash memory is provided with either both the current sector address and the sector specific memory cell address or only the sector specific memory cell address for generating the memory cell address.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Deboleena Minz Sakalley, Rakesh Pandey
  • Microelectromechanical system devices having through substrate vias and methods for the fabrication thereof
    Patent number: 8883535
    Abstract: Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) device are provided. In one embodiment, the MEMS device fabrication method includes forming a via opening extending through a sacrificial layer and into a substrate over which the sacrificial layer has been formed. A body of electrically-conductive material is deposited over the sacrificial layer and into the via opening to produce an unpatterned transducer layer and a filled via in ohmic contact with the unpatterned transducer layer. The unpatterned transducer layer is then patterned to define, at least in part, a primary transducer structure. At least a portion of the sacrificial layer is removed to release at least one movable component of the primary transducer structure. A backside conductor, such as a bond pad, is then produced over a bottom surface of the substrate and electrically coupled to the filled via.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor Inc.
    Inventor: Lianjun Liu
  • Incident capacitive sensor
    Patent number: 8884241
    Abstract: A capacitive sensor device for measuring radiation. The device includes two sensor regions and top plate structure. The sensor regions are of a material that generates electron-hole pairs when radiation strikes the material. A separation region is located between the two sensor regions. The capacitance between a sensor region and top plate is dependent upon radiation striking the sensor region. A blocking structure selectively and differentially blocks radiation having a parameter value in a range from the sensor region so as to differentially impact electron-hole pair generation of one sensor region with respect to electron-hole pair generation of the other sensor region at selected angles of incidence of the radiation.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Gate driver with desaturation detection and active clamping
    Patent number: 8885310
    Abstract: Apparatus, systems, and methods are provided for protecting a switching device using a gate driver device. An exemplary gate driver system includes an interface for coupling to a switching device, a desaturation detection arrangement coupled to the interface to detect a desaturation condition based on an electrical characteristic at the interface, and a deactivation arrangement coupled to the interface to deactivate the switching device in a manner that is influenced by the electrical characteristic at the interface. In one embodiment, the switching device is deactivated by providing a deactivation current to a control terminal of the switching device and adjusting the deactivation current based on an electrical characteristic at the interface.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ibrahim S. Kandah
  • System and method for fetching information in response to hazard indication information
    Patent number: 8886895
    Abstract: A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Itay Peled, Moshe Anschel, Jacob Efrat, Alon Eldar, Ziv Zamsky
  • Circuit simulation acceleration using model caching
    Patent number: 8886508
    Abstract: A mechanism for improving speed of simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having identical properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, then output values of the previously-evaluated transistor or device are used in calculating the output values of the present transistor or device.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kiran Kumar Gullapalli, Steven D. Hamm
  • Leadframes, air-cavity packages, and electronic devices with offset vent holes, and methods of their manufacture
    Patent number: 8884413
    Abstract: A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philip H. Bowles, Stephen R. Hooper
  • Semiconductor device having a nanotube layer and method for forming
    Patent number: 8883639
    Abstract: A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer. A seed layer is deposited over the first dielectric layer and in the first opening. A layer is formed of conductive nanotubes from the seed layer over the first dielectric layer and over the first opening. A second dielectric is formed over the layer of conductive nanotubes. An opening is formed in the second dielectric layer over the first opening. Conductive material is deposited in the second opening.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Douglas M. Reber
  • TESTING AN ELECTRICAL CONNECTION OF A DEVICE CAP
    Publication number: 20140329344
    Abstract: A method of testing a device includes setting a potential of a cap terminal of the device to a first voltage, setting a potential of a self test plate of the device to a testing voltage, and detecting a first displacement of a proof mass of the device when the cap terminal is set to the first voltage and the self test plate is set to the testing voltage. The method includes setting a potential of the cap terminal of the device to a second voltage, detecting a second displacement of the proof mass of the device when the cap terminal is set to the second voltage and the self test plate is set to the testing voltage, and comparing the first displacement and the second displacement to evaluate an electrical connection between the cap terminal and a cap of the device.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Peter S. Schultz
  • Methods and apparatus for an ISFET
    Patent number: 8878257
    Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: November 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna