Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

Abstract: A method of erasing a non-volatile memory (NVM) array includes determining a first number based on a temperature of the NVM array. Erase pulses of the first number are applied to the NVM array. A first verify of the NVM is performed for a first time after commencing the applying after the first number has been reached.

Abstract: A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.

Abstract: An active device region is formed in and on a semiconductor substrate. An interconnect layer is formed over the active device region, wherein the interconnect layer comprises a first dielectric material having a first dielectric constant, a first metal interconnect in the first dielectric material, and a second metal interconnect in the first dielectric material and laterally spaced apart from the first metal interconnect. A portion of the first dielectric material is removed such that a remaining portion of the first dielectric material remains within the interconnect layer, wherein the removed portion is removed from a location between the first and second metal interconnects. The location between the first and second metal interconnects from which the portion of the first dielectric material was removed is filled with a second dielectric material having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant.

Abstract: A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package.

Abstract: A method for making a packaged integrated circuit is provided. The method includes making a first panel of encapsulated die. In some embodiments, if a threshold number of die are not positioned in proper positions in the first panel, the die are separated from the first panel. The separated die are subsequently encapsulated in other panels of encapsulated die. Conductive interconnects can be formed over the other panels. The other panels are then separated into integrated circuit packages.

Abstract: A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.

Abstract: A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

Abstract: A method for managing power of a battery powered handheld audio device by receiving an indicia of signal quality for a received continuous-time radio signal. The method compares the indicia of signal quality to a signal threshold. Upon a favorable comparison, enacting a first analog signal conditioning setting. Upon an unfavorable comparison, enacting a second analog signal conditioning setting. The method further provides, upon the favorable comparison, disabling a digital filtering operation, and upon the unfavorable comparison, enabling the digital filtering operation.

Abstract: A system for monitoring and controlling the power of a Radio Frequency (RF) signal in a short-range RF transmitter. An RF signal-generation unit generates the RF signal. A power amplifier amplifies the RF signal. An impedance-matching network matches the output impedance of the power amplifier to input impedance of an antenna. One or more RF power monitors monitor the voltage amplitude of the RF signal at the output of at least one of the RF signal-generation unit, the power amplifier and the impedance-matching network. The one or more RF power monitors further generate at least one alarm signal, based on the voltage amplitude of the RF signal. A control unit modifies at least one operating parameter of at least one of the RF signal-generation unit and the power amplifier, based on the at least one alarm signal generated by the one or more RF power monitors.

Abstract: An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is arranged to enable dynamic configuration of a value of a core identifier of at least one of the processing cores of the first and at least one further types.

Abstract: A method of soft programming a non-volatile memory (NVM) array includes determining a first number based on a temperature of the NVM array and applying the first number of soft program pulses to a section of the NVM array. A first soft program verify of the section of the NVM array is then performed for a first time after completing the applying the first number of soft program pulses.

Abstract: A method of making a semiconductor device includes forming a split gate memory gate structure on a memory region of a substrate, and protecting the split gate memory gate structure by depositing protective layers over the memory region including the memory gate structure and over a logic region of the substrate. The protective layers include a material that creates a barrier to diffusion of metal. The protective layers are retained over the memory region while forming a logic gate in the logic region. The logic gate includes a high-k dielectric layer and a metal layer. A spacer material is deposited over the logic gate. Spacers are formed on the memory gate structure and the logic gate. The spacer on the logic gate is formed of the spacer material and the spacer on the memory gate structure is formed with one of the protective layers.

Abstract: A self adjusting reference for an input buffer including an adjustable voltage shifter, a comparator, and a comparator and adjust circuit. The voltage shifter provides adjustable reference voltages based on a primary reference voltage, including upper, midway, and lower reference voltages. The comparator compares the midway reference voltage with the input voltage to provide an input sense signal indicative of a voltage state of the input voltage. The comparator and adjust circuit increases voltage levels of the reference voltages when the input voltage is in a low voltage state and has a voltage level that is greater than the lower reference voltage, and decreases the voltage levels of the reference voltages when the input voltage is in a high voltage state and has a voltage level that is less than the upper reference voltage.

Abstract: Methods and systems are disclosed for making temperature-based adjustments to bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store temperature-based bias condition information in storage circuitry. The disclosed embodiments select and apply bias conditions for the NVM cells based upon temperature measurements.

Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a cellular network. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in multiple cellular networks.

Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.

Abstract: A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces.

Abstract: A method of optimising the operation of a WLAN device which is used in the transmission and reception of a service over a medium includes determining a the value of a collision avoidance metric of the chip set at a specific time; predicting the available bandwidth of the WLAN from the value of the metric; determining the current data rate of the WLAN based on predicted available bandwidth and the type of service; and selecting a power amplifier bias voltage that is the minimum permitted for the determined current data rate to reduce the power consumption of the WLAN device.

Abstract: A voltage regulator including first and second regulator elements connected between an output node and a supply rail for supplying load current to a load connected to the output node. The voltage regulator includes first and second control modules for controlling the first and second regulator elements respectively to maintain the output node at a regulated voltage in the presence of a variable impedance presented by the load to the output node, the second regulator element and the second control module having a smaller load current capacity and smaller leakage current than the first regulator element and the first control module. The voltage regulator includes a mode selector for de-activating the first regulator element and the first control module in a first operational mode, for activating the first regulator element and the first control module in a second operational mode.