Abstract: An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.

Abstract: Startup circuits with native transistors. In some embodiments, a startup circuit may include a first inverter configured to receive a bandgap voltage (Vbg) from a bandgap reference circuit and to produce an output voltage (VOUT), and a second inverter operably coupled to the first inverter to form a latch, the latch configured to maintain a value of VOUT, the second inverter including a native transistor, the native transistor having a gate terminal coupled to VOUT and a source terminal coupled to Vbg. In other embodiments, a method may include receiving Vbg at a startup circuit and outputting VOUT configured to change in response to Vbg rising above Vtrig or falling below Vtrig, where the power consumption of the startup circuit is based at least in part upon a voltage value applied to a source terminal of a native transistor within the startup circuit.

Abstract: A device includes a Doherty amplifier having a main path and a peaking path. The Doherty amplifier includes a main amplifier configured to amplify a signal received from the main path and a peaking amplifier configured to amplify a signal received from the peaking path when the signal received from the peaking path exceeds a predetermined threshold. The device includes a first driver amplifier connected to the main path of the Doherty amplifier. The first driver amplifier is configured to exhibit an amplitude and phase distortion characteristic that is an inverse of an amplitude and phase distortion characteristic of the main amplifier. The device includes a second driver amplifier connected to the peaking path of the Doherty amplifier. The second driver amplifier is configured to exhibit an amplitude and phase distortion characteristic that is an inverse of an amplitude and phase distortion characteristic of the peaking amplifier.

Abstract: An apparatus (36) includes a motion amplification structure (52), an actuator (54), and a sense electrode (50) in proximity to the structure (52). The actuator (54) induces an axial force (88) upon the structure (52), which causes a relatively large amount of in-plane motion (108) in one or more beams (58, 60) of the structure (52). When sidewalls (98) of the beams (58, 60) exhibit a skew angle (28), the in-plane motion (108) of the beams (58, 60) produces out-of-plane motion (110) of a paddle element (62) connected to the end of the beams (58, 60). The skew angle (28), which results from an etch process, defines a degree to which the sidewalls (98) of beams (58, 60) are offset or tilted from their design orientation. The out-of-plane motion (110) of element (62) is sensed at the electrode (50), and is utilized to determine an estimated skew angle (126).

Abstract: A MEMS device (20) includes a proof mass structure (26) and beams (28, 30) residing in a central opening (32) of the proof mass structure (26), where the structure and the beams are suspended over a substrate (22). The beams (28, 30) are oriented such that lengthwise edges (34, 36) of the beams are beside one another. Isolation segments (38) are interposed between the beams (28, 30) such that a middle portion (40) of each of the beams is laterally anchored to adjacent isolation segments (38). The isolation segments (38) provide electrical isolation between the beams. The beams (28, 30) are anchored to the substrate (22) via compliant structures (61, 65) that isolate the beams from deformations in the underlying substrate. The compliant structures (61, 65) provide electrically conductive paths (96, 98) to the substrate (22) for the beams (28, 30) where the paths are electrically isolated from one another.

Abstract: A microprocessor comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event, determine if at least one reset condition has been met upon detection of the reset event, and cause at least a part of the microprocessor to remain in a reset state upon determining that the at least one reset condition has been met.

Abstract: Apparatus are provided for amplifier systems and related integrated circuits are provided. An exemplary integrated circuit includes a main amplifier arrangement, first impedance matching circuitry coupled between the output of the main amplifier arrangement and a first output of the integrated circuit, a peaking amplifier arrangement, and second impedance matching circuitry coupled between the output of the peaking amplifier arrangement and a second output of the integrated circuit. In one exemplary embodiment, the first impedance matching circuitry and the second impedance matching circuitry have different circuit topologies and different physical topologies.

Abstract: A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result.

Abstract: In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic. A second data line pair is coupled to the first bit line pair via second switching logic and to the second bit line pair via third switching logic. If a row address match but not a column address match exists between a first and second access address, the second switching logic selectively connects the second data line pair with the first bit line pair based on a first decoded signal generated from the column address of the second access address and the third switching logic decouples the second data line pair from the second bit line pair.

Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.

Abstract: A fluid cooled semiconductor die package includes a package support substrate with a die mounting surface and an opposite package mounting surface. The package support substrate has external connector solder deposits on respective external connector pads of the package mounting surface, and a package fluid inlet duct and a package fluid outlet duct each providing fluid communication between the die mounting surface and package mounting surface. A semiconductor die is mounted on the die mounting surface. The die has external terminals electrically connected to the external connector pads. An inlet solder deposit is soldered to an inlet pad of the package mounting surface. The inlet pad surrounds an entrance of the fluid inlet duct. An outlet solder deposit is soldered to an outlet pad of the package mounting surface. The outlet pad surrounds an exit of the package fluid inlet duct.

Abstract: A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.

Abstract: In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic and to the third bit line pair via second switching logic, and a second data line pair is coupled to the second bit line pair via third switching logic and to the fourth bit line pair via fourth switching logic. If a match exists between at least portions of a first and second access address, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair.

Abstract: A mold chase for packaging a semiconductor die includes first and second toothed mold clamps, each having teeth, recesses located between the teeth, and an open cavity located in a center of the first mold clamp. The second mold clamp is in facing arrangement with the first mold clamp and the teeth in the first mold clamp mate with corresponding recesses in the second mold clamp and vice-versa. In an open position a lead frame can be inserted into one of the first or second mold clamps and in a closed position, the teeth and recesses of the first and second mold clamps bend leads of the lead frame into two spaced, planar rows.

Abstract: A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.

Abstract: A clock multiplexer includes first and second input stages for outputting first and second clock signals, respectively. The first and second input stages each include a flip-flop, a latch and a first logic gate. Reset terminals of the flip-flops receive a select signal based on which the first and second input stages output the first and second clock signals. A second logic gate is connected to the first and second input stages for selectively providing the first and second clock signals as an output clock signal.

Abstract: A voltage level shifter for translating a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The voltage level shifter comprises an input port for receiving the binary input signal as an input voltage varying between a first input voltage level and a second input voltage level. An output port is connected to a node for outputting the binary output signal as an output voltage varying between a first output voltage level and a second output voltage level. A supply voltage node connectable to a voltage supply, can provide the second output voltage level. A first switch is arranged to couple the supply voltage node to the node and to decouple the supply voltage node from the node based on a voltage at the node. A feedback voltage loop is connected to the node for providing a feedback voltage based on the voltage at the node.

Abstract: A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units.