Abstract: A battery charging circuit that stabilizes operation when switching between charge modes includes first and second transistors. The first transistor has a source connected to a first switch circuit. The first switch circuit connects the second transistor to either one of first and second external terminals. A mode switch circuit generates a switch signal for switching from a trickle charge mode to a fast charge mode. The mode switching circuit provides the switching signal to a comparison circuit. After a predetermined time elapses, the mode switching circuit provides the switching signal to the switch circuit. The comparison circuit lowers a current restriction reference voltage, which determines a charging current value, and returns the current restriction reference voltage to its original value after switching modes.

Abstract: A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.

Abstract: An over-current protection circuit, including a current input for receiving a input current and a current output electrically connectable to a load, for outputting an output current proportional to the input current. A switch connects the current input to the current output. The switch has at least two switch states including an open state in which a current flow from the current input to the current output is interrupted and a closed state in which the current flow is enabled. The switch includes a switch control input for controlling the switch state. The circuit has a sensor for sensing a load current applied to the load and a controller connected to the sensor for controlling the switch to be in the open state when the sensed load current has exceeded a current threshold during a predetermined period of time, the predetermined period of time being dependent on an amount with which said sensed load current exceeds the threshold.

Abstract: In an integrated circuit, a state of a switch coupled to the integrated circuit is determined by comparing a switch voltage at a first terminal of the switch to a reference voltage at a first time. If the switch voltage is higher than the reference voltage, the switch is determined to be in a first state. If the switch voltage is lower than the reference voltage, the switch voltage is stored in a storage element to produce a stored voltage. The stored voltage is compared to the switch voltage at a second time after the first time. A determination is made that the switch is in the first state if the switch voltage is higher than the stored voltage at the second time. A determination is made that the switch is in a second state if the switch voltage is not higher than the stored voltage at the second time.

Abstract: A semiconductor device comprising timer logic for generating a first modulated waveform signal, and delay logic, operably coupled to the timer logic and arranged to provide a first delay in a rising edge of the first modulated waveform signal generated by the timer logic; and provide a second delay in a falling edge of the first modulated waveform generated by the timer logic. The first delay and second delay of the first modulated waveform forms a second, refined modulated waveform signal that comprises a higher frequency resolution than a frequency resolution of the first modulated waveform signal.

Abstract: An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35?) with gates (38, 38?) coupled to one or more bias supplies Vb, Vb?. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb?. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

Abstract: A measurement circuit and method for measuring a quiescent current of a circuit under test are provided. The measurement circuit comprises: a comparator having a first input terminal for receiving a reference voltage, a second input terminal coupled to the circuit under test, and an output terminal; a current source having a first terminal coupled to a first power supply voltage terminal, and a second terminal for providing a current to the circuit under test; a first switch having a first terminal coupled to the second terminal of the current source, a second terminal coupled to the circuit under test, and a control terminal coupled to the output terminal of the comparator; and a first counter having a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving a clock signal, and an output terminal for providing a first counter value associated with the quiescent current.

Abstract: An LDMOSFET transistor (100) is provided which includes a substrate (101), an epitaxial drift region (104) in which a drain region (116) is formed, a first well region (107) in which a source region (112) is formed, a gate electrode (120) formed adjacent to the source region (112) to define a first channel region (14), and a grounded substrate injection suppression guard structure that includes a patterned buried layer (102) in ohmic contact with an isolation well region (103) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region (107) and from the drain region (116), where the buried layer (102) is disposed below the first well region (107) but not below the drain region (116).

Abstract: Disclosed are example techniques for frame-based power management in a light emitting diode (LED) system having a plurality of LED strings. A voltage source provides an output voltage to drive the LED strings. An LED driver generates a frame timing reference representative of the frame rate or display timing of a series of image frames to be displayed via the LED system. An update reference is generated from the frame timing reference. The LED driver monitors one or more operating parameters of the LED system. In response to update triggers marked by the update reference, the LED driver adjusts the output voltage of the voltage source based on the status of each of the one or more monitored operating parameters (either from the previous update period or determined in response to the update trigger), thereby synchronizing the updating of the output voltage to the frame rate (or a virtual approximation of the frame rate) of the video being displayed.

Abstract: A system and method for modifying an information unit, the method includes the following stages: (i) receiving, over a first bus, a request to initiate a snooping type atomic operation associated with at least one information unit located at a first address of a memory module; (ii) providing the information unit over the first bus; (iii) attempting to complete the snooping type atomic operation of an updated information unit; and (iv) defining the atomic operation as a failed atomic operation if during at least one stage of receiving, providing and attempting, the first address was locked as a result of a locking type atomic operation.

Abstract: A switching power converter converts an input DC voltage to an output DC voltage using a switch to selectively connect an input DC voltage energy source. A switching controller controls the switch. A pulse width modulation centering signal is generated by a spread spectrum clock signal generator. An error amplifier of the switching controller generates an analog error signal based on a switching voltage measured after the switching of the switching power converter, the output voltage of the switching power converter, the pulse width modulation centering signal and a reference. A pulse width modulated signal generator generates the pulse width modulation signal to control the switch of the switching power converter based on the pulse width modulation centering signal and the analog error signal.

Abstract: A method and a communication device for processing ATM cells. The communication device includes an input interface adapted to receive an ATM cell that is associated with a PHY value and includes a pair of VCI and VPI fields. The communication device is characterized by comprising a search unit, adapted to search, within a group of memory entries that belong to a memory unit, for a pair of VCI and VPI fields that have values that match the values of the VCI and VPI fields of the received ATM cell, if the received VCI field and VPI fields belong to a first predefined group of VCI and VPI fields. The communication device further includes a processor, connected to the search unit, wherein the processor is adapted to determine a channel identifier of the received ATM cell in response to a result of the search and in response to a PHY value associated with the received ATM cell.

Abstract: A target circuit of an electronic device is placed in a suspended mode by disconnecting the target circuit from one or more voltage sources. A refresh controller periodically initiates a refresh operation during the suspended mode by temporarily reconnecting the target circuit to the one or more voltage sources for a duration sufficient to recharge capacitances of the target circuit. The refresh controller terminates the refresh operation by disconnecting the target circuit from the one or more voltage sources, thereby continuing the suspended mode of the electronic device. The refresh controller can employ a Very Low Frequency Oscillator (VLFO) to time the frequency of refresh operations. The VLFO manages the refresh initialization timing based on the voltage across a capacitor that is selectively charged or discharged so as to implement the refresh operation. The refresh controller further can employ a counter to time the duration of the refresh operation.

Abstract: Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the data and, in response to a read access at the memory address, are employed to check for errors in both the address and the data provided in response to the read access (the read data). The ECC checkbit generation process can result, for particular memory addresses, in checkbits that can incorrectly indicate whether errors are present in the read data. Accordingly, the checkbits can be selectively inverted based on the memory address so that the checkbit pattern will not result in an incorrect error detection or correction.

Abstract: Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.

Abstract: A discrete time sigma-delta modulator apparatus for class-D operation comprises a feed-forward path having an input at one end thereof and an output at another end thereof. A first summation unit is coupled in the feed-forward path to a first integrator. A quantizer is coupled in the feed-forward path after the first integrator and a feedback path arrangement is coupled to an input of the first summation unit. A low pass filter is arranged in the feedback path arrangement so as only to drive the first integrator.

Abstract: A device includes a first test port coupled to a first test device, a second test port coupled to a second test device, a resource, and a security controller coupled to the first and second test ports. The security controller is operable to authenticate the first test device prior to authenticating the second test device, and, in response to authenticating the first test device, permit the first and second test devices to access the first resource.

Abstract: A Schmitt trigger circuit having a test circuit and method for testing are provided. The Schmitt trigger test circuit includes switches for reconfiguring the Schmitt trigger for testing by shorting the input and output terminals of an inverter and by opening a feedback path to allow the application of test voltages to the gates of feedback transistors coupled to the inverter. The method includes: directly connecting an input terminal of the inverter to an output terminal of the inverter; providing a first power supply voltage to the feedback transistors coupled to the inverter; measuring a first voltage at the input terminal; removing the first power supply voltage from the feedback transistors; providing a second power supply voltage to the feedback transistors. The test circuit and method reduce the test time by eliminating the need to ramp an input voltage while monitoring the output.

Abstract: A system includes a first processor, a second processor, a first clock coupled to the first processor, and a third clock coupled to the first processor and to the second processor. The first processor includes debug circuitry coupled to receive the third clock, synchronization circuitry coupled to receive the first clock, wherein the synchronization circuitry receives a first request to enter a debug mode and provides a first synced debug entry request signal and wherein the first synced debug entry request signal is synchronized with respect to the first clock, and an input for receiving a second synced debug entry request signal from the second processor wherein the first processor waits to enter the debug mode until the first synced debug entry request signal and the second synced debug entry request signal are both asserted.

Abstract: An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.