Patents Assigned to Freescale
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Patent number: 8860001Abstract: A resistive random access memory (ReRAM) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer inlcudes the first metal. The ReRAM further includes a second metal layer over the metal-oxide layer and a first continuous conductive barrier layer in physical contact with sidewalls of the first metal layer and of the metal-oxide layer.Type: GrantFiled: April 9, 2012Date of Patent: October 14, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Cheong Min Hong, Ko-Min Chang, Feng Zhou
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Patent number: 8860596Abstract: A redundant signed digit (RSD) analog to digital converter (ADC) includes an amplifier, a first variable capacitance circuit coupled to a first input to the amplifier, a second variable capacitance circuit coupled to a second input to the amplifier, a third variable capacitance circuit coupled to a first output of the amplifier, and a fourth variable capacitance circuit coupled to a second output of the amplifier. An output of the third and fourth capacitance circuits are coupled to one another and to inputs to the first and second variable capacitance circuits. Capacitance values of the first, second, third and fourth variable capacitance circuits are higher when inputs to the ADC correspond to a selected number of more significant bits than when inputs to the ADC correspond to a remaining number of less significant bits.Type: GrantFiled: August 20, 2013Date of Patent: October 14, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Robert S. Jones, Peijun Wang
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Publication number: 20140300193Abstract: A power safety circuit comprises a power sense terminal; an output terminal; an output driver unit connected to the output terminal; an input terminal connectable to receive a first power from a power source and arranged to supply the first power to the output driver unit; and a power detection unit arranged to detect a state of the input terminal and provide a power sense signal to the power sense terminal; wherein the power sense terminal is arranged to supply a second power to the output driver unit when the power sense signal indicates a level of the first power below a minimum level for driving the output terminal. An integrated circuit device comprises at least one power safety circuit. A safety critical system comprises at least one integrated circuit device with at least one power safety circuit.Type: ApplicationFiled: October 27, 2011Publication date: October 9, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Philippe Givelin, Valerie Bernon-Enjalbert, Guillaume Founaud
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Publication number: 20140302641Abstract: A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.Type: ApplicationFiled: June 1, 2014Publication date: October 9, 2014Applicant: Freescale Semiconductor, IncInventors: Kesvakumar V.C. Muniandy, Navas Khan Oratti Kalandar
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Publication number: 20140299935Abstract: A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.Type: ApplicationFiled: June 19, 2014Publication date: October 9, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Konstantin V. Loiko, Toni D. Van Gompel, Rode R. Mora, Michael D. Turner, Brian A. Winstead, Mark D. Hall
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Publication number: 20140303804Abstract: A method of controlling a thermal budget of an integrated circuit device is described. The method comprises obtaining a first junction temperature measurement value for the integrated circuit device at a first time instant, and a further junction temperature measurement value for the integrated circuit device at a further time instant. The method further comprises calculating a prospective junction temperature value for the integrated circuit device at a future time instant based at least partly on the first and further junction temperature measurement values; and configuring an operating condition of the integrated circuit device based at least partly on the calculated prospective junction temperature value.Type: ApplicationFiled: November 4, 2011Publication date: October 9, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Michael Priel, Roy Drucker, Dan Kuzmin
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Publication number: 20140300615Abstract: A memory access controller for managing data flow between a memory unit and a processing unit is described. The memory access controller comprises an addressing unit and an unpacking unit. The addressing unit may receive an address from said processing unit and select a data location within said memory unit in dependence on that address. The unpacking unit may read a first word from the selected data location, unpack the first word into a second word by applying a data conversion scheme which depends on the received address, and provide the second word to the processing unit. The data conversion scheme may comprise, for at least one possible address, a pixel format conversion. A data processing system and a method are also proposed.Type: ApplicationFiled: November 24, 2011Publication date: October 9, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Michael Staudenmaier, Vincent Aubineau, Juergen Frank
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Patent number: 8853792Abstract: Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.Type: GrantFiled: January 5, 2012Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Murshed M. Chowdhury, James K. Schaeffer
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Patent number: 8856705Abstract: A method can include identifying a device design comprising first and second instantiations of a device, identifying a layer of the device design, identifying a first region of the device design for the first instantiation based on the layer of the first instantiation, and a second region of the device design for the second instantiation based on the layer of the second instantiation. identifying a first compare layer of the device design that comprises a plurality of first compare features including a first compared feature within the first region and a second compared feature within the second region, determining a difference between the first compared feature and the second compared feature, and determining if the difference meets a tolerance to determine if the first instantiation matches the second instantiation.Type: GrantFiled: May 8, 2012Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Mehul D. Shroff, Sanjay R. Parihar, Edward O. Travis
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Patent number: 8856198Abstract: Embodiments of methods and systems for producing random values include a first module that provides a random data request (e.g., a request for an unspecified length of random data) to a random number generator. The random number generator generates random data in response to the random data request, and multiple random values derived from the random data are stored in a buffer. In response to receiving a request for a random value (e.g., an initialization vector), the first module produces the random value based on the multiple random values stored in the buffer. The system also may be configured to receive requests for other types of random values, and to fulfill those requests using random data that is not buffered (e.g., random data that is received directly from the random number generator in response to a request for a specified length of random data).Type: GrantFiled: March 30, 2012Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: David G. Abdoo, Matthew W. Brocker, Steven D. Millman, Thomas E. Tkacik
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Patent number: 8853058Abstract: A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.Type: GrantFiled: June 22, 2012Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Kesvakumar V. C. Muniandy, Navas Khan Oratti Kalandar, Lan Chu Tan
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Patent number: 8853027Abstract: In one aspect, a disclosed method of fabricating a split gate memory device includes forming a gate dielectric layer overlying an channel region of a semiconductor substrate and forming an electrically conductive select gate overlying the gate dielectric layer. The method further includes forming a counter doping region in an upper region of the substrate. A proximal boundary of the counter doping region is laterally displaced from a proximal sidewall of the select gate. The method further includes forming a charge storage layer comprising a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region and forming an electrically conductive control gate adjacent to the vertical portion of the charge storage layer and overlying the horizontal portion of the charge storage layer.Type: GrantFiled: October 1, 2012Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Cheong Min Hong, Sung-Taeg Kang
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Patent number: 8853780Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.Type: GrantFiled: May 7, 2012Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Won Gi Min, Zhihong Zhang, Jiang-Kai Zuo
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Patent number: 8853795Abstract: A semiconductor device comprises a substrate provided with a doping of a first type, on which an electronic circuit is provided surrounded by a circuit portion of the substrate provided with a doping of a second type; at least one pad for connecting the electronic circuit to an external device outside the substrate, surrounded by a pad portion provided with a doping of the second type; a sensing device comprising a sensor portion of the substrate provided with a doping of the first type, for sensing a parameter forming a measure for a local electrical potential of the substrate; and an evaluation unit connected to the sensing device, for providing an evaluation signal based on a difference between the parameter and a reference value.Type: GrantFiled: February 23, 2009Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Hubert Bode, Andreas Laudenbach, Andreas Roth
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Patent number: 8856587Abstract: A data processing device includes a cache having a plurality of cache lines. Each cache line has a lockout state that indicates whether an error has been detected for data accessed at the cache line. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. When a cache line is in a locked-out state, the cache line is not used by the cache. Accordingly, a locked-out cache line is not employed by the cache to satisfy a cache accesses, and is not used to store data retrieved from memory in response to a cache miss. In response to determining the detected error likely did not result from a hardware failure or other persistent condition, memory error management software can reset the lockout state of the cache line.Type: GrantFiled: May 31, 2011Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventor: William C. Moyer
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Patent number: 8854049Abstract: A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit.Type: GrantFiled: September 25, 2007Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Florian Bogenberger, Leos Chalupa
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Patent number: 8853867Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.Type: GrantFiled: January 31, 2014Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Sheila F. Chopin, Varughese Mathew, Leo M. Higgins, III, Chu-Chung Lee
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Patent number: 8855962Abstract: A system for testing electronic circuits includes first, second, and third standard interfaces. A test port master and a test port slave are connected to an external testing apparatus. The first, second, and third standard interfaces are tested in first, second, and third test modes, respectively. The tests are initiated by asserting a test mode activate and first, second, and third test mode enable signals, respectively, which enable reuse of test patterns across different electronic circuits.Type: GrantFiled: February 22, 2012Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventor: Deepak Jindal
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Patent number: 8853840Abstract: A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically conductive die mount is molded onto upper surface areas of each inner lead external connection section. A semiconductor die is mounted on the non-electrically conductive die mount and bond wire provide interconnects for selectively electrically connecting bonding pads of the die to the inner lead bonding sections and at least one outer lead bonding section. A mold compound covers the semiconductor die, the bond wires, and the outer and inner lead bonding sections.Type: GrantFiled: February 21, 2013Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Yin Kheng Au, Pey Fang Hiew, Jia Lin Yap
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Patent number: 8855129Abstract: A method for transmitting packets, the method includes receiving multiple packets at multiple queues. The method is characterized by dynamically defining fixed priority queues and weighted fair queuing queues, and scheduling a transmission of packets in response to a status of the multiple queues and in response to the definition. A device for transmitting packets, the device includes multiple queues adapted to receive multiple packets. The device includes a circuit that is adapted to dynamically define fixed priority queues and weighted fair queuing queues out of the multiple queues and to schedule a transmission of packets in response to a status of the multiple queues and in response to the definition.Type: GrantFiled: June 7, 2005Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Boaz Shahar, Freddy Gabbay, Eyal Soha
