Abstract: A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive operation if the first DMA task was not completed during the first DMA task execution sub-interval. A device having a first DMA task controlling capabilities, the device includes a memory unit; characterized by including a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval.

Abstract: Apparatus are provided for converting a discrete-time analog signal to a continuous-time analog signal. A module comprises a digital-to-analog converter and a filtering arrangement coupled between the digital-to-analog converter and an output node. The digital-to-analog converter converts a digital signal to a discrete-time analog signal. The filtering arrangement comprises a forward signal arrangement having an input configured to receive the discrete-time analog signal and a feedback signal arrangement coupled to the forward signal arrangement. The feedback signal arrangement generates a discrete-time feedback signal at the input of the forward signal arrangement based on one or more continuous-time analog signals from the forward signal arrangement. The forward signal arrangement generates the continuous-time analog output signal at the output node based on a difference between the discrete-time analog signal and the discrete-time feedback signal.

Abstract: A system for providing an output clock signal, the system includes: (a) a first clock divider, adapted to receive an input clock signal and to provide a first divider output clock signal having a frequency that is lower than a frequency of the input clock signal; and (b) a second clock divider, adapted to select a second divider input clock signal out of the input clock signal and the first divider output clock signal, and to provide the output clock signal having a frequency that is lower than the frequency of the second divider input clock signal.

Abstract: A current sensor having a pair of sense transistors is disclosed. The sense transistors sense a current conducted by a power transistor of a voltage regulator. The ratio in size between the power transistor and the sense transistors corresponds to a scaling factor M. Each sense transistor has an associated series connected sense resistor. The two sense resistors are unbalanced and provide a differential voltage based on the sensed current at the sense transistor to a transconductor. The transconductor has heavy emitter degeneration to provide an output current substantially proportional to the current conducted by the primary power transistor, the proportion determined by the scaling factor M and a ratio of the emitter degeneration and sense resistors.

Abstract: To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.

Abstract: A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer.

Abstract: An arbiter for a device arranged to be coupled to a serial bus, the arbiter comprising a means for obtaining identifier information associated with one more other devices coupled to the serial bus and; means for determining a priority level based upon an identifier associated with the device and identifier associated with one of the other devices.

Abstract: A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface thereof, wherein the smallest dimension (width) across said feature is less than ?200 nm, a conductive layer being present on at least a portion of said surface, (b) filling said recessed feature with a conductive material, and (c) prior to filling said recessed feature with said conductive material, treating said surface with an accelerator.

Abstract: A demodulator in a receiver includes a correlator (240) for de-spreading a spread-spectrum signal, and a decision module (250) for detecting a preamble and for synchronizing to data frames of the spread spectrum signal. The demodulator includes symbol timers (231 and 233) that allow the demodulator to correlate to two preamble symbols simultaneously, where the two preamble symbols occur one-half a symbol period apart. The correlator includes a correlator structure having taps that correct for any frequency offset of a carrier signal. The correlator correlates to each of the two preamble symbols a plurality of times through oversampling, where each correlation compensates for a different amount of frequency offset. By analyzing occurrence of peaks in magnitude of the correlations, the decision module detects the preamble and selects weights for the taps to de-spread data frames received after the preamble.

Abstract: A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.

Abstract: In a wireless 802.15.4 communication system, a method and system are provided for switching between a predetermined protocol transmission mode and a high-speed transmission mode by including signaling mode information in a data packet (330, 340) to instruct the receiver device (300) to demodulate at least a data payload using the predetermined transmission mode if the signaling mode information comprises a first predetermined value, and to demodulate at least the data payload using the high-speed transmission mode if the signaling mode information comprises a second predetermined value. The signaling mode information may be included in the SFD field of an 802.15.4 SHR structure to instruct the receiver how to demodulate or process the data packet, or may be included as desired anywhere in the data packet to instruct the receiver how to demodulate or process one or more subsequent data packets.

Abstract: An embodiment of a die assembly includes a flange, lip walls, and leads for electrical contact with one or more die mounted on the flange. The flange has first and second opposed flange surfaces and flange sidewalls extending between the surfaces. The lip walls have first and second opposed lip surfaces and lip sidewalls extending between the first and second lip surfaces. The lip sidewalls are positioned adjacent to the flange sidewalls. The leads, which have inboard end portions and outboard end portions, are configured to preserve a seating plane. The seating plane is spaced apart from a plane of the second flange surface. The inboard end portions of the leads are embedded in the lip walls, and extend from the seating plane upward through the lip walls toward the first lip surfaces. The outboard end portions are aligned substantially within the seating plane.

Abstract: A data processing system and method includes a data processor and memory that are coupled to debug circuitry that generates debug messages including address translation trace messages. A memory management unit (MMU) includes a translation lookaside buffer (TLB) for implementing address translation to translate addresses between virtual and physical forms. The debug circuitry includes message generation circuitry coupled to the MMU for receiving notice when TLB entries are modified and generating both an address translation trace message and a corresponding program correlation message containing at least one of branch history information and instruction count information. The branch history information is a history of direct branch instructions that are executed and whether, when executed, the direct branch instructions were taken. The instruction count information is a count of one or more data processing instructions executed up to a point in time when a new TLB entry is established in the TLB.

Abstract: A system and method for processing signals in a communication system is disclosed herein. The system and method comprises processing steps and processing logic for generating a downlink subframe comprising a preamble and a plurality of data bursts within a predetermined frequency band; embedding first and second sets of downlink subframe parameters in the downlink subframe; transmitting the downlink subframe; receiving the downlink subframe; processing data in the preamble to obtain channel quality indicator (CQI) information; and using the CQI information to select either the first set or set second set of downlink subframe parameters to process the data bursts in the downlink subframe.

Abstract: A system for dispensing an underfill material between an integrated circuit (IC) chip and a substrate includes a platform at which the underfill material is supplied. The IC chip and the substrate are mounted at the periphery of the platform. The platform rotates and facilitates the movement of the underfill material toward the IC chip and the substrate. The system further includes a Bernoulli tube that is located proximate to the IC chip and the substrate. The Bernoulli tube generates a low pressure in the proximity of the IC packages. The low pressure facilitates the dispensing of the underfill material between the IC chip and the substrate.

Abstract: A wireless communication unit comprises a transmitter having an analogue feedback power control loop having a power control function arranged to set an output power level of the transmitter. The power control function comprises a predictor sub-system arranged to reduce sensitivity to loop latency of the analogue feedback power control loop. The use of a predictor sub-system provides reduced sensitivity to loop latency, gain variations and delay.

Abstract: A memory system for an I/O controller which includes a memory with multiple memory blocks, a supply voltage control circuit providing power to each memory block, and control logic. Each memory block retains stored information with reduced power consumption when receiving a reduced voltage level. The control logic allocates buffers in the memory and controls the supply voltage control circuit to provide the full voltage level to at least one memory block of at least one allocated buffer and to provide the reduced voltage level to remaining memory blocks. Each memory block includes one or more buffers. In various embodiments the control logic fully powers each memory block of a buffer or less than all of the memory blocks. A linked buffer structure may be used to reduce the memory blocks of an allocated buffer receiving full power, such as only one memory block in the buffer.

Abstract: A calibration signal generator for use in a balancing circuit calibration device in a radio receiver, the calibration signal generator comprising: a means of amplifying a clocking signal from a clocking signal generator to provide a first calibration signal; a means of generating a second calibration signal from the clocking signal, the first and second calibration signals being transmissible to a one or more mixing circuits in the balancing circuit calibration device; and a means synchronising the operation of other circuit elements in the balancing circuit calibration device with the clocking signal; characterised in that the clocking signal generator is present in the radio receiver and used therein for other functions.

Abstract: The present invention relates to a method and apparatus for conditioning a polishing pad used in chemical mechanical polishing in which a consistent pressing force can be provided between an abrasive conditioning member and the polishing pad. Specifically, a moveable weight member is provided that can be selectively moved along a length of a support arm in the conditioning apparatus. The position of the weight member relative to the position at which the abrasive conditioning member is mounted alters the resultant pressing force in view of the change in moment created. In a particular example, the positioning of the weight member can be automatically controlled using a drive mechanism controlled by a control unit, such as a computer.

Abstract: An entrapment prevention and detection device for an opening/closing mechanism detects entrapment with a simple structure and does not occupy much space. When a foreign object, such as a human body part approaches a window glass, such as an automobile window, the capacitance of a capacitive sensor increases. A control circuit compares a most recent capacitance obtained by a capacitance detection circuit with a previous value and if the most recent capacitance value is greater than the previous value, when the glass is being raised (closed), the control circuit determines that a foreign object has approached the glass and then stops or lowers (opens) the glass.