Abstract: In one embodiment, a method of forming a via includes providing a semiconductor substrate, wherein the semiconductor substrate comprises a through-via region, forming isolation openings and a sacrificial feature in the through-via region, filling the isolation openings to form isolation regions, forming a dielectric layer over the semiconductor substrate after filling the isolation openings, forming a first portion of a through-via opening in the dielectric layer, forming a second portion of the through-via opening in the semiconductor substrate, wherein forming the second portion of the through-via opening comprises removing the sacrificial feature, and forming a conductive material in the first portion and the second portion of the through-via opening.

Abstract: A circuit includes a first resistive element coupled to a diode, a second resistive element, a first transistor having a first current electrode coupled the second resistive element, a second transistor having a first current electrode coupled to the first resistive element and a second current electrode coupled to the control electrode of the first transistor, a third resistive element coupled to a node, a third transistor having a first current electrode coupled to the node and having a control electrode and a second current electrode each coupled to the control electrode of the second transistor, a fourth transistor having a first current electrode coupled to the second resistive element and a control electrode coupled to the control electrode of the second transistor, and a fifth transistor having a first current electrode coupled to the node and a control electrode coupled to the second current electrode of the fourth transistor.

Abstract: A tool for forming a desired pattern on a polishing pad establishes a vibration that is coupled to the polishing pad. The vibration removes small portions of the polishing pad according to the desired pattern. The polishing pad is then used in a chemical mechanical polishing (CMP) step to polish a layer on a semiconductor device.

Abstract: A device and method for processing information fragments, the method includes: receiving multiple information fragments from multiple communication paths; wherein the each information fragment is associated with a cyclic serial number indicating of a generation time of the information fragment; storing the multiple information fragments in multiple input queues, each input queue being associated with a communication path out of the multiple communication paths; determining whether at least one serial number associated with at least one valid information fragment positioned in a head of one of the multiple input queues is located within a pre-rollout serial number range; mapping, in response to the determination, serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues to at least one serial number range that differs from the pre-rollout serial number range; and sending to an output queue information fragment metadata associated with a minimal v

Abstract: A switching circuit includes first and second transistors, and a driver circuit. The first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a control electrode. The driver circuit has an input for receiving an input signal, and an output coupled to the control electrode of the first transistor. The driver circuit precharges the control electrode of the first transistor to a first predetermined voltage, and in response to the input signal transitioning from a first logic state to a second logic state, the driver circuit provides a second predetermined voltage to the control electrode of the first transistor to cause the first transistor to be conductive.

Abstract: A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

Abstract: Snoop requests are managed in a data processing system having a cache coupled to a processor that provides access addresses to the cache. Snoop queue circuitry provides snoop addresses to the cache via an arbiter. The snoop queue circuitry has a snoop request queue for storing a plurality of entries. Each entry of the snoop request queue that corresponds to a snoop request includes a snoop address and a corresponding status indicator. The corresponding status indicator indicates whether the snoop request has zero or more collapsed snoop requests having a common snoop address which have been merged to form the snoop request. The status indicator is used for debug and by fullness management logic to manage the capacity of the snoop request queue. A general collapsed status signal is generated to indicate whenever any snoop queue entry collapsing occurs.

Abstract: A method of attaching a solder ball to a bonding pad includes disposing flux on the bonding pad, attaching a conductive metal ring to the pad using the flux, and placing the solder ball in the ring. A reflow operation is performed that secures the ring to the pad and melts the solder ball into and around the ring. A solder joint is formed between solder ball and the pad, with the ring secured within the ball. Use of the ring allows for higher stand-off height to be achieved with similar solder ball size, without having to use bigger ball size as in the conventional method, which causes solder ball bridging. With higher stand-off height, better board level reliability performance can be obtained.

Abstract: A bit stream is received and each bit corresponding to the bit stream is over-sampled to generate a first set of data samples. Each data sample from the first set of data samples is compared with a corresponding immediate previous data sample to generate a second set of data samples. The second set of data samples is compared with bit masks, and accordingly, some of the data samples in the first set of data samples are identified for replacement. Further, a substitute data sample is selected from the first set of data samples based on a predefined criterion and some of the data samples in the first set of data samples are replaced with the substitute data sample.

Abstract: A clock buffer for a clock network that reduces leakage current and lowers power consumption. The clock buffer includes a first CMOS transistor, a second CMOS transistor, and a leakage current prevention circuit connected to the first and second CMOS transistors. The leakage current prevention circuit includes a first PMOS transistor, which is connected between the source of a PMOS transistor of the first CMOS transistor and a power supply line, and a second PMOS transistor, which is connected between the source of a PMOS transistor of the second CMOS transistor and the power supply line. The first and second PMOS transistors are deactivated in response to an enable signal generated when a circuit block does not require the clock signal. The first and the second PMOS transistors have predefined widths and lengths such that the addition of these transistors in series with the CMOS transistors does not increase the propagation delay of the clock buffer circuit.

Abstract: A method for forming a semiconductor device includes providing a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. After the providing the first cap wafer and second cap wafer, the second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. After the bonding the second cap wafer to the device wafer, a vacuum is applied, wherein during the applying the vacuum, a sealing layer is formed over the first cap wafer, wherein the sealing layer seals the first opening.

Abstract: A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.

Abstract: A technique for calibrating a transceiver of a wireless communication device includes selectively coupling an output node of a transmitter of the transceiver to an input node of a receiver of the transceiver. A calibration signal is provided, from the output node of the transmitter, to the input node of the receiver. The calibration signal is down-converted, with the receiver, to provide a down-converted calibration signal. A discrete Fourier transform is performed on the down-converted calibration signal. Finally, one or more correction factors are determined based on an analysis of the discrete Fourier transform of the down-converted calibration signal. At least one of the correction factors is utilized to facilitate substantial cancellation of a direct current offset associated with the transceiver.

Abstract: An electrical circuit for manipulating at least one of a voltage and a current on a bus wire comprises a first switch having a first gate, a first source, and a first potential reduction unit. The first potential reduction unit is suitable for lowering a potential difference between the first gate and the first source of the first switch, wherein the lowering of the potential difference is caused by a shutting-off of a first control voltage.

Abstract: A system comprises a first signal processing logic module and at least one further signal processing logic module. The system further comprises mismatch handler logic module arranged to detect a mismatch between outputs of the first and at least one further signal processing logic module, the mismatch between outputs indicating a failed operation. The mismatch handler logic module further arranged, upon detection of a mismatch between outputs of the first and at least one further signal processing logic module, to analyse internal states of the first and at least one further signal processing logic module, determine whether the cause of the output mismatch is due to a transient fault, and upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronise the first and at least one further signal processing logic module.

Abstract: A method and a device for reducing noise induced errors. The device includes: a latch that includes a latch input node; a voltage limiting transfer circuit connected between a first input node and between the latch; wherein the voltage limiting transfer circuit is adapted to selectively transfer an input signal from the first input node to the latch during transfer mode; and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range.

Abstract: A circuit comprises a first amplifier portion and a second amplifier portion. The first amplifier portion includes first and second transistors coupled together in a common-base configuration. A current mirror is coupled to the first and second transistors. A first filter is coupled between a first input and the first and second transistors. The second amplifier portion includes third and fourth transistors coupled together in a common-base configuration. First and second current sources are coupled to the third and fourth transistors. A second filter is coupled between a second input and the control electrodes of the third and fourth transistors, wherein the first and second filters are coupled together.

Abstract: An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (1) using a double side adhesive tape (2), and then sequentially depositing an insulating layer (15) and a conductive shielding layer (16) before encapsulating the modules with a molding compound (17). After removing the adhesive tape (2) to expose a surface of the encapsulated modules, a multi-layer circuit substrate (100) is formed over the exposed surface, where the circuit substrate includes shielding via structures (101-112) that are aligned with and electrically connected to the conductive shielding layer (16), thereby encircling and shielding the circuit module(s).

Abstract: A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.

Abstract: A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel.