Patents Assigned to Freescale
  • Publication number: 20110233693
    Abstract: A micro or nano electromechanical transducer device formed on a semiconductor substrate comprises a movable structure which is arranged to be movable in response to actuation of an actuating structure. The movable structure comprises a mechanical structure comprising at least one mechanical layer having a first thermal response characteristic and a first mechanical stress response characteristic, at least one layer of the actuating structure, the at least one layer having a second thermal response characteristic different to the first thermal response characteristic and a second mechanical stress response characteristic different to the first mechanical stress response characteristic, a first compensation layer having a third thermal response characteristic and a third mechanical stress characteristic, and a second compensation layer having a fourth thermal response characteristic and a fourth mechanical stress response characteristic.
    Type: Application
    Filed: November 25, 2009
    Publication date: September 29, 2011
    Applicants: Freescale Semiconductor, Inc, COMMISSARIAT A LENGERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: François Perruchot, Emmanuel Defay, Patrice Rey, Lianjun Liu, Sergio Pacheco
  • Patent number: 8026760
    Abstract: A switched capacitor circuit utilizes a pair of serially connected differential amplifiers that have plus inputs, minus inputs, plus outputs, and minus outputs. Feedback to the plus/minus inputs is in a first configuration relative to the output of the pair of differential amplifiers in a sampling mode and a second configuration in a hold mode. Similarly, the plus/minus inputs relative to the plus/minus outputs of the serially connected differential amplifiers is reversed between the sampling and hold modes.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: September 27, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ammisetti V. Prasad
  • Patent number: 8028178
    Abstract: A universal serial bus power control circuit including at least one first switch which selectively couples a power source node to an external power node, a comparator which detects when the external power node is charged, a feedback node for enabling voltage regulation, a charge circuit and a controller. The charge circuit charges the external power node from the power source node and selectively couples the feedback node to at least one of the power source node and the external power node. The controller opens the first switch when the external power node is not charged, controls the charge circuit to charge the external power node while coupling the feedback node to the power source node, and closes the first switch and couples the feedback node to the external power node in a host mode when the external power node is charged.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: September 27, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Siddhartha GK, David M. Schlueter, Richard T. Unetich
  • Patent number: 8026700
    Abstract: In a D.C. to D.C. converter, an input voltage is received via an inductor at an input terminal and stored onto a capacitor of an integrator. A first switch is coupled between the input terminal and a reference terminal such as ground and thereby fluxes the inductor. The input voltage stored on the capacitor falls at a rate determined by the integrator circuit and an initial value of the input voltage. After a time duration, the first switch becomes nonconductive. Current flows from the inductor through a diode to an output terminal until a second switch across the diode is made conductive. Stored voltage on the capacitor of the integrator increases in response to the second switch being conductive. The stored voltage on the capacitor is continuously compared with a reference voltage. The second switch is made nonconductive when the stored voltage on the capacitor exceeds the reference voltage.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: September 27, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: John M. Pigott
  • Publication number: 20110227229
    Abstract: A method of processing a semiconductor wafer is provided which comprises treating a metallisation layer provided on a backside of the wafer to form a plurality of channels therein, such that at least some of the channels along substantially the length thereof extend through the thickness of the metallisation layer to the backside of the wafer, thereby exposing the material of the backside of the wafer. When the semiconductor wafer is separated into dies, each die is provided with a plurality of channels, which extend to an edge of the die. On attaching the die to a die attach flag by solder, the solder does not stick to the exposed material of the backside of the die, and channels are thereby formed in the solder. This allows venting of gases formed in the solder, and decreases void formation in the solder.
    Type: Application
    Filed: April 27, 2007
    Publication date: September 22, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Robert Bauer, Anton Kolbeck
  • Publication number: 20110227146
    Abstract: A transistor power switch device comprising a semiconductor body presenting opposite first and second faces, an array of vertical field-effect transistor elements for carrying current between the first and second faces, is provided. The array of transistor elements comprises at the first face an array of source regions of a first semiconductor type, at least one body region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the second transistor region, and a conductive layer contacting the source regions and insulated from the control electrode by at least one insulating layer.
    Type: Application
    Filed: November 27, 2008
    Publication date: September 22, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Jean Michel Reynes, Beatrice Bernoux, Rene Escoffier, Pierre Jalbaud, Ivana Deram
  • Patent number: 8021957
    Abstract: An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Venkat R. Kolagunta, Mehul D. Shroff
  • Patent number: 8021970
    Abstract: A method includes forming a first dielectric layer over a substrate; forming nanoclusters over the first dielectric layer; forming a second dielectric layer over the nanoclusters; annealing the second dielectric layer using nitrous oxide; and after the annealing the second dielectric layer, forming a gate electrode over the second dielectric layer.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinmiao J. Shen, Cheong M. Hong, Sung-Taeg Kang, Marc A Rossow
  • Patent number: 8022505
    Abstract: A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philippe Renaud, Patrice Besse, Amaury Gendron
  • Patent number: 8022507
    Abstract: An improved varactor diode is obtained by providing a substrate having a first surface and in which are formed a first N region having a first peak dopant concentration located at a first depth beneath the surface, and a first P region having a second peak dopant concentration greater than the first peak dopant concentration located at a second depth beneath the surface less than the first depth, and a second P region having a third peak dopant concentration greater than the second peak dopant concentration and located at a third depth at or beneath the surface less than the second depth, so that the first P region provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge of the second P region up to the second peak dopant concentration.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vishal P. Trivedi
  • Patent number: 8021926
    Abstract: Electronic elements (40) with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes (411), preferably dielectric lined, in front sides (523) of substrates (52?), filling the trenches or pipes with a conductor (54) having a coefficient of expansion not too different from that of the substrate (52?) but of higher conductivity, forming an epitaxial SC layer (64) over the front side (523) of the substrate (52?) in Ohmic contact with the conductor (54) in the trenches or pipes (411), forming various semiconductor (SC) devices (42, 80) in the epi-layer (64), back grinding the substrate (52?) to expose bottoms (548) of the conductor filled trenches or pipes (41), and providing a back-side conductor (524) contacting the conductor (54) in the trenches or pipes (411). For silicon SCs, tungsten is a suitable conductor (54) for filling the trenches or pipes (411) to minimize substrate stress.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edouard de Frésart, Robert W. Baird
  • Patent number: 8023457
    Abstract: In a closed-loop wireless communication system, a codebook-based precoding feedback compression mechanism is provided to remove redundancy from the precoding feedback that is caused by channel correlation in time and frequency. Redundancy due to temporal correlation of the transmission channel is removed by sending precoding feedback only if there is a change in the precoder state for the channel to the receiver. Redundancy due to frequency correlation is removed by run length encoding the precoding feedback, thereby compressing the precoding feedback prior in the frequency domain. By compressing the precoding feedback, the average rate of precoder feedback is reduced.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jayesh H. Kotecha, Kaibin Huang
  • Patent number: 8024620
    Abstract: A translated address and an untranslated address associated with a same processor operation are received. An address-type indicator is provided whose value is indicative of whether the translated or untranslated address is to be used for creating a debug message. The value of the address-type indicator is selectively modified in response to occurrence of one or more selected debug events. Based at least in part on the value of the address-type indicator, the translated or untranslated address is selected. The address-type indicator may be selectively overridden to select the translated or untranslated address as the selected address based on whether a process identifier is at least one of a set of process identifiers or whether at least one of the translated or untranslated address falls within one or more predetermined address ranges. A debug message is created using at least a portion of the selected address.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William C. Moyer
  • Patent number: 8022850
    Abstract: Embodiments include DACs and methods for digital-to-analog conversion. A DAC includes an encoder and a plurality of DAC elements. The encoder maps each of a plurality of bits of a digital input value to one of the DAC elements, and produces a sign indication indicating whether a magnitude of the digital input value is above or below a threshold. Each DAC element produces a DAC element analog output signal that indicates whether a received sign indication and a received bit corresponds to a first state, a second state or a third state (e.g., a zero, positive or negative state). In an embodiment, the DAC uses positive historic mapping information when the magnitude of the digital input value is above the threshold, and negative historic mapping information when the magnitude of the digital input value is below the threshold. DAC elements may be configurable into a Return-to-Zero or a Non-Return-to-Zero mode.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Bruce M. Newman
  • Patent number: 8020443
    Abstract: A microelectromechanical systems (MEMS) transducer (90) is adapted to sense acceleration in mutually orthogonal directions (92, 94, 96). The MEMS transducer (90) includes a proof mass (100) suspended above a substrate (98) by an anchor system (116). The anchor system (116) pivotally couples the proof mass (100) to the substrate (98) at a rotational axis (132) to enable the proof mass (100) to rotate about the rotational axis (132) in response to acceleration in a direction (96). The proof mass (100) has an opening (112) extending through it. Another proof mass (148) resides in the opening (112), and another anchor system (152) suspends the proof mass (148) above the surface (104) of the substrate (98). The anchor system (152) enables the proof mass (148) to move substantially parallel to the surface (104) of the substrate (98) in response to acceleration in at least another direction (92, 94).
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yizhen Lin, Andrew C. McNeil
  • Publication number: 20110221469
    Abstract: A logic built-in self test (LBIST) system comprises a device under test having a first plurality of first bistable multivibrator circuits an LBIST controller, and a second plurality of second bistable multivibrator circuits. Each second bistable multivibrator circuit is coupled to a corresponding first bistable multivibrator circuit to swap a second state value kept by the second bistable multivibrator circuit with a first state value kept by the corresponding first bistable multivibrator circuit depending on a first control signal from the LBIST controller and the second bistable multivibrator circuits are coupled to form one or more scan chains when receiving a second control signal from the LBIST controller.
    Type: Application
    Filed: November 24, 2008
    Publication date: September 15, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Rolf Schlagenhaft
  • Publication number: 20110223956
    Abstract: A method of allocating a plurality of communication channels of a network, for a plurality of network stations of the network. The method comprises generating a common transmission message for the plurality of network stations and transmitting the generated transmission message to the plurality of network stations. The message comprises channel allocation information allowing an allocation of channels by the network stations, the information relating to each of the plurality of network stations. A network managing station for communicating with the plurality of network stations, there being a plurality of communication channels available for use by the plurality of network stations. The network managing station comprises a processor, arranged to generate the common transmission message for the plurality of network stations and a transmitter arranged to transmit the generated transmission to said plurality of networks.
    Type: Application
    Filed: November 28, 2008
    Publication date: September 15, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Mathieu Villion, Jean-Marie Voisin, Volker Wahl
  • Publication number: 20110221307
    Abstract: A micro or nano electromechanical transducer device formed on a semiconductor substrate comprises a movable structure which is arranged to be movable in response to actuation of an actuating structure. The movable structure comprises a mechanical structure having at least one mechanical layer having a first thermal response characteristic, at least one layer of the actuating structure having a second thermal response characteristic different to the first thermal response characteristic, and a thermal compensation structure having at least one thermal compensation layer. The thermal compensation layer is different to the at least one layer and is arranged to compensate a thermal effect produced by the mechanical layer and the at least one layer of the actuating structure such that the movement of the movable structure is substantially independent of variations in temperature.
    Type: Application
    Filed: November 25, 2009
    Publication date: September 15, 2011
    Applicants: Freescale Semiconductors, Inc., COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lianjun Liu, Sergio Pacheco, Francois Perruchot, Emmanuel Defay, Patrice Rey
  • Publication number: 20110222712
    Abstract: An audio output circuit includes an on-chip left channel amplifier module, an on-chip center channel amplifier module, and an on-chip right channel amplifier module. A left channel IC pin is operably coupled to an output of the on-chip left channel amplifier module. A right channel IC pin is operably coupled to an output of the on-chip right channel amplifier module. A center channel IC pin is operably coupled to an output of the on-chip center channel amplifier module. A center channel feedback IC pin is operably coupled to an input of the on-chip center channel amplifier module to provide a feedback loop. A left jack connection is operably coupled to the left channel IC pin. A right jack connection is operably coupled to the right channel IC pin. A jack return connection coupled to the center feedback IC pin. An inductor has a first node coupled to the jack return connection and a second node coupled to the center channel IC pin.
    Type: Application
    Filed: May 24, 2011
    Publication date: September 15, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Matthew D. Felder
  • Patent number: 8020067
    Abstract: A method for locating an end of a received frame includes providing hypothetical trellis paths that end at different possible end points, performing a CRC check for each hypothetical trellis path, calculating a false detection variable for hypothetical trellis paths that passed the CRC check, and determining the end point of the received frame in response to the calculations.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: September 13, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dov Levenglick, Ron Bercovich, Eliezer Zand