Abstract: A system and method for dynamically migrating stash transactions include first and second processing cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), and an operating system (OS) scheduler. The first core executes a first thread associated with a frame manager. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers to indicate scheduling-out and scheduling-in of the first thread from the first core and to the second core. The STMMU uses the pre-empt notifiers to enable dynamic stash transaction migration.

Abstract: During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being selectively flushed from the trace FIFO based on a state of the FIFO before the trace information has been communicated to a trace analyzer.

Abstract: A method of fabricating a bipolar transistor including emitter and base regions having first and second conductivity types, respectively, includes forming an isolation region at a surface of a semiconductor substrate, the isolation region having an edge that defines a boundary of an active area of the emitter region, and implanting dopant of the second conductivity type through a mask opening to form the base region in the semiconductor substrate. The mask opening spans the edge of the isolation region such that an extent to which the dopant passes through the isolation region varies laterally to establish a variable depth contour of the base region.

Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.

Abstract: A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.

Abstract: During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being flushed from the trace FIFO before the trace information has been communicated to a trace analyzer.

Abstract: An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate.

Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.

Abstract: Systems and methods for thermally enhanced electronic component packaging with through mold vias are described. In some embodiments, a method may include forming one or more vias through an encapsulant with a laser, each of the one or more vias having one end proximal a top surface of an electronic component covered by the encapsulant and another end proximal an outer surface of the encapsulant. The method may also include inserting a thermally conductive material into the one or more vias, providing a heat spreader over the outer surface of the encapsulant, the heat spreader thermally coupled to the thermally conductive material, and reflowing the thermally conductive material.

Abstract: A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.

Abstract: A method (80) entails providing (82) a structure (117), providing (100) a controller element (102, 24), and bonding (116) the controller element to an outer surface (52, 64) of the structure (117). The structure includes a sensor wafer (92) and a cap wafer (94). Inner surfaces (34, 36) of the wafers (92, 94) are coupled together, with sensors (30) interposed between the wafers (92, 94). One wafer (94, 92) includes a substrate portion (40, 76) with bond pads (42) formed on its inner surface (34, 36). The other wafer (94, 92) conceals the substrate portion (40, 76). After bonding, methodology (80) entails forming (120) conductive elements (60) on the element (102, 24), removing (126) material sections (96, 98, 107) from the wafers (92, 94, 102) to expose the bond pads (42), forming (130) electrical interconnects (56), applying (134) packaging material (64), and singulating (138) to produce sensor packages (20, 70).

Abstract: A heterogeneous multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. A debug control circuit is connected between the first and second TAP controllers and the first and second debug ports. Based on external configuration signals, the debug control circuit configures the connections between the first and second TAP controllers and the first and second debug ports according to predetermined configuration modes, which allows flexibility in debugging the heterogeneous multi-core integrated circuit.

Abstract: A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorize the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritize respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.

Abstract: A data processing system (10) includes a first master (14) and a second master (16 or 22). The first master includes a cache (28) and snoop queue circuitry (44, 52, 54) having a snoop request queue (44) which stores snoop requests. The snoop queue circuitry receives snoop requests for storage into the snoop request queue and provides snoop requests from the snoop request queue to the cache, and the snoop queue circuitry provides a ready indicator indicating whether the snoop request queue can store more snoop requests. The second master includes outgoing transaction control circuitry (72) which controls initiation of outgoing transactions to a system interconnect.

Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, intrinsic base and collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: In one or more embodiments, an echo reduction system can include multiple adaptive filters operable to provide estimated echo replicas based on received signal information coupled to respective multiple adders that can combine a send signal and outputs of the respective adaptive filters and can provide respective output combinations to a filter selector. The filter selector can select from the outputs of the adders and provide a selected output as output for the echo reduction system. In one or more embodiments, the filter selector can control signal processing of the filters by providing control signal to the adaptive filters, where the control signals can indicate to ones of the adaptive filters to pause or continue signal processing. In one or more embodiments, the echo reduction system can include at least one delay unit that can delay receive signal information to at least one of the adaptive filters.

Abstract: Systems and methods are provides that access a tag cell file in computer storage media, wherein the tag cell file is associated with a abstract representation of a component to be included in a semiconductor device. The tag cell file includes a tag that identifies the component as being based on intellectual property of a third party. The abstract representation of the component is translated to a computer data file for manufacturing the semiconductor device. The tag associated with the component is included in the data file, and the data file may be parsed by accounting programs to determine the extent of usage of the intellectual property in the semiconductor device.

Abstract: A semiconductor device comprises processing logic arranged to execute program instructions. The semiconductor device further comprises signature generation logic arranged to receive at least one value from at least one internal location of the semiconductor device, and to generate a current signature value, based on the at least one received value. Validation logic is arranged to validate the current signature value generated by the signature generation logic. The processing logic is further arranged, upon execution of a signature validation instruction, to enable the validation of the current signature value provided by the validation logic.

Abstract: A method (90) entails placing (124) sensor elements (122) in an array (126) arranged to correspond with locations of controller dies (24) in a controller wafer (94) and encapsulating (128) the array (126) in a mold material (74) to form a panel (130) of the sensor elements (122). The sensor elements (122) include bond pads (42) that are concealed by a material section (116, 118) of the sensor elements (122). The controller wafer (94) is bonded (134) to the panel (130) to form a stacked wafer structure (136). After bonding, methodology (90) entails forming (140) conductive elements (60) on the controller wafer (95), removing material sections (100) from the controller wafer (94) and removing the material sections (116, 118) from the sensor elements (122) to expose the bond pads (42), forming (148) electrical interconnects (56), applying (152) packaging material (64), and singulating to produce sensor packages (20, 76).

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.