Abstract: The present invention relates to an integrated device, comprising a semiconductor device formed on a semiconductor substrate, a temperature sensing element formed within a semi-conductive layer formed on the semiconductor substrate, an electrically insulating layer formed over the semi-conductive layer, a metal layer formed over the insulation layer and forming an electrical contact of the semiconductor device, and a thermal contact extending from the metal layer through the electrically insulating layer to a first region of the semi-conductive layer, wherein the first region of the semi-conductive layer is electrically isolated from the temperature sensing element. The present invention also relates to a method of forming a temperature sensing element for integration with a semiconductor device.

Abstract: A method for locating an end of a received frame includes providing hypothetical trellis paths that end at different possible end points, performing a CRC check for each hypothetical trellis path, calculating a false detection variable for hypothetical trellis paths that passed the CRC check, and determining the end point of the received frame in response to the calculations.

Abstract: A method and apparatus for reducing power consumption of transistor-based circuit is disclosed. The method includes receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit. The apparatus is adapted to receive a low power mode indication, and includes: a determining circuit to determine whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and a power gating, adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination.

Abstract: A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor.

Abstract: A method for power reduction, the method includes determining whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively providing power to at least a portion of a component of an integrated circuit during a low power mode. A device having power reduction capabilities, the device includes power switching circuitry, and a power management circuitry adapted to determine whether to power down at least the portion of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power.

Abstract: A method of operating a circuit, including operating in a first mode, wherein in the first mode, a first power domain operates in an active power mode and a second power domain operates in an active power mode, wherein in the first mode, a first set of at least one terminal of a first circuit of the first power domain are coupled to a second set of at least one terminal of a second circuit of the second power mode via an isolation circuit for providing signals from the first circuit to the second circuit, is provided. The method further includes operating the circuit in a second mode, wherein in the second mode, the first power domain operates in a power gated mode and a second power domain operates in an active power mode.

Abstract: A method for manufacturing a high quality semiconductor device having a through via structure. A substrate is manufactured with an oxide layer including a window region in a region in which a through via is formed. The substrate is bonded with another substrate to form an SOI substrate. The SOI substrate is ground to reduce its thickness. An island region is formed in a region at which a TSV (Through Silicon Via) structure is formed. A device and a TSV are coupled by a wire. The silicon substrate at a bottom side of the SOI substrate is removed to expose the island region from the bottom. A back contact for the TSV is formed in the window region, which is formed in a buried oxide layer.

Abstract: A method and an adjustable clamp system for clamping a die assembly during wire bonding. The system includes at least one pair of opposing base walls, each of the base walls has a base clamping surface. There is at least one pair of clamping members, each one of the clamping members being movable towards a respective base clamping surface to thereby clamp a lead frame of the die assembly. A die assembly support is disposed between the pair of opposing base walls and the die assembly support and pair of opposing base walls provide a cavity. There is a position sensor coupled to a controller and there is also a drive that is controllable by the controller. The drive provides movement of the die assembly support relative to each the base clamping surface to thereby adjust a depth of the cavity.

Abstract: A method and system allow a mobile subscriber to block reception of mobile terminated (MT) Short Message System (SMS) messages yet still have the ability to send outgoing mobile originated SMS messages. The method and system include determining whether a MT SMS feature setting is enabled or disabled at an SMS layer of a protocol stack of the mobile device and transmitting a mobile device registration message to a mobile network service center as SMS capable or incapable, depending on the MT SMS feature setting. The mobile device may be registered as SMS incapable by setting certain fields within information elements of registration messages. If a MT SMS message is received and the MT SMS feature setting is disabled, then the SMS layer may increment a blocked message counter and transmit a failure message to the service center. The service center may be included in a base station of the mobile network.

Abstract: A voltage reference module of an integrated circuit device includes a current source to apply a current to a set of voltage cells, thereby generating a voltage drop across each cell. The voltage cells are configured such that the individual voltage drop associated with each cell in response to the application of the current is relatively stable over a temperature range. The voltage reference module generates a voltage based on the voltage drops across the voltage cells, and therefore the generated voltage is also stable over the temperature range. Bypass switches can be connected across each voltage cell whereby the switches can be individually opened and closed to include or exclude cells in generation of the reference voltage. In an embodiment, the switches are set during a trimming process for the integrated circuit device so that the voltage reference module provides a specified voltage.

Abstract: In the field of battery charging for electronic devices, it is known to employ a number of measures to avoid excessive power dissipation by a pass device in a charging system. However, many of these measures are either incompatible with linear charging regimes or add cost to the adapter and/or charging system. The present invention provides a power dissipation measurement circuit for controlling a control device that acts in series with another, but maximum current limiting, control device to control drive current to the pass device so as to limit the power dissipated by the pass device to a maximum threshold value.

Abstract: A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO). The method includes, in a training mode: (1) setting a control voltage of the VCO at a first voltage level; (2) increasing the control voltage of the VCO from the first voltage level to a second voltage level, until a loss of the feedback signal is detected; and (3) storing an indicator value corresponding to the second voltage level of the control voltage of the VCO. The method further includes, in a normal mode: (1) monitoring a voltage level of the control voltage of the VCO by generating a monitored indicator value corresponding to the voltage level of the control voltage of the VCO; and (2) asserting the loss of feedback signal based on a comparison of the monitored indicator value and the indicator value.

Abstract: A frequency multiplier circuit, comprising a first stage including a first differential pair of amplifier elements having respective current conduction paths connected in parallel between first and second nodes and respective control terminals connected to receive input signals of opposite polarity at an input frequency in the radio frequency range, the first and second nodes being connected to respective bias voltage supply terminals through first and second impedances respectively so that current flowing differentially in the current conduction paths of the first differential pair of amplifier elements produces a voltage difference across the first and second nodes at a frequency which contains a harmonic of the input frequency, and a second stage including a second differential pair of amplifier elements coupled at the harmonic of the input frequency with the first and second nodes to amplify differentially the voltage difference and produce an output signal at the harmonic of the input frequency.

Abstract: A received signal having pilots is converted to a first signal in the frequency domain having the pilots. The pilots are extracted from the first signal to obtain extracted pilots to form a second signal. The second signal is used to provide a first estimate of a channel. The first estimate is converted to the time domain. Noise is removed from the first estimate in the time domain to provide a second estimate of the channel in the time domain. An autocorrelation of the channel in the frequency domain is determined using the second estimate of the channel. Extension signals are determined using the autocorrelation. The extension signals are appended to the first estimate of the channel to obtain a third estimate of the channel. The third estimate is used to provide a data signal in the frequency domain.

Abstract: A wireless communication unit comprises a transmitter having an analogue feedback power control loop with an input and a power amplifier having a power amplifier output, where the analogue feedback power control loop is arranged to feedback a signal to the input to set an output power level of the transmitter. The wireless communication unit further comprises an outer digital loop operably coupled from the power amplifier output to the transmitter. In this manner, the inner analogue loop is used to linearise a response obtained from the power amplifier and an outer digital loop wherein the outer digital loop controls the inner analogue loop with regard to saturation detection and correction as well as facilitating multi-mode operation of the wireless communication unit.

Abstract: A decoding circuit includes a mixed modulation memory access circuit responsive to burst rejection information. The mixed modulation memory access circuit selectively accesses burst memory locations containing a valid burst of coded bits. The mixed modulation memory access circuit selectively avoids accessing burst memory locations containing a rejected burst of coded bits based on the burst rejection information. In one example, the mixed modulation memory access circuit accesses the valid burst when the burst rejection information indicates that the memory location contains valid bursts. In one example, the mixed modulation memory access circuit generates zero confidence information when the burst rejection information indicates that the memory location contains rejected bursts.

Abstract: A method for packaging a semiconductor die or assembling a semiconductor device that includes a heat spreader begins with attaching the heat spreader to a film and dispensing a mold compound in granular form onto the film such that the mold compound at least partially covers the film and the heat spreader. The film with the attached heat spreader is placed in a first mold section. A substrate having a semiconductor die attached and electrically coupled to it are placed in a second mold section and then the first and second mold sections are mated such that the die is covered by the heat spreader. The granular mold compound is then melted so that the mold compound covers the die and sides of the heat spreader. The first and second mold sections then are separated. The film, which adheres to the substrate, is removed to expose a top surface of the heat spreader, and thus a semiconductor device is formed.

Abstract: Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

Abstract: A free-space communication system and method of operation includes a first communication device physically coupled to a substrate and having an optical transmitter for communicating information. A second communication device is physically coupled to the substrate and has an optical receiver for communicating information. An adjustable optical beam deflector is physically coupled to the substrate for optically coupling the first communication device and the second communication device via an optical beam including a free-space optical portion. A feedback system includes a non-optical communication link for receiving information regarding the optical beam. The feedback system controls the adjustable optical beam deflector to direct the optical beam to improve the quality of an optical link incorporating the optical beam.

Abstract: An audio output circuit includes an on-chip left channel amplifier module, an on-chip center channel amplifier module, and an on-chip right channel amplifier module. A left channel IC pin is operably coupled to an output of the on-chip left channel amplifier module. A right channel IC pin is operably coupled to an output of the on-chip right channel amplifier module. A center channel IC pin is operably coupled to an output of the on-chip center channel amplifier module. A center channel feedback IC pin is operably coupled to an input of the on-chip center channel amplifier module to provide a feedback loop. A left jack connection is operably coupled to the left channel IC pin. A right jack connection is operably coupled to the right channel IC pin. A jack return connection coupled to the center feedback IC pin. An inductor has a first node coupled to the jack return connection and a second node coupled to the center channel IC pin.