Abstract: A semiconductor device comprising an interface logic module for transmitting data frames across an interface, and controller logic module arranged to control a rate at which the interface logic transmits data across the interface. Upon receipt of data frames to transmit across the interface, the controller logic module is arranged to determine a sequence of data rates with which to transmit sequential data frames across the interface, and to configure the transmission of the data frames across the interface according to the determined data rate sequence. The selection of these data rates will be dependent on specific critical RF frequencies where EMI impacts have to be minimized.

Abstract: A method of time resolved radiation assisted device alteration testing of a semiconductor circuit which includes performing spatially resolved radiation assisted circuit testing on the semiconductor circuit while applying a test pattern to determine a pass-fail modulation location, asynchronously scanning the semiconductor circuit with radiation while repeatedly applying the test pattern and providing pass-fail results, combining corresponding pass-fail results provided during the asynchronously scanning to determine a shifted pass-fail modulation indication, determining time shift information between the pass-fail modulation location and the shifted pass-fail modulation indication, and identifying at least one of the test vectors based on the time shift information. The radiation may be a continuous wave laser beam.

Abstract: A sample-and-hold circuit (100) is provided that that includes a sample-and-hold switch (125), an integrator circuit (180) designed to generate an output voltage (VOUT) signal, and a bias voltage (VBIAS) source (185). The sample-and-hold switch (125) incldues a first switch (130), a second switch (140), and a third switch (150). The first switch (130) has a first gate (132), a first source (134) and a first drain (134), the second switch (140) has a second gate (142), a second source (144) electrically coupled to a bulk region (147), and a second drain (146), and the third switch (150) has a third gate (152), a third drain (154), and a third source (156) coupled to the first source (136). The integrator circuit (180) includes an output operational amplifier (170) having an inverting input (V?) (172) coupled to the second drain (146) and a non-inverting input (V+).

Abstract: A system includes a platform domain implementing address-indexed operations and an application domain implementing application context-oriented operations. The platform domain includes a platform interconnect to process address-indexed platform transactions and a trace monitor to generate a debug trace stream from platform transactions based on their platform context information. The application domain includes a processing component and a queue manager to queue descriptors for data frames to be processed by the application domain, each descriptor having application context information including application-specific debug information for the corresponding data frame.

Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The apparatus includes a hardware module, adapted to receive at least one indication of a load of the system and to determine a voltage level and a clock signal frequency to be provided to the system, and a software module, adapted to configure a voltage source and a clock signal source in response to the determination. The method includes: (i) receiving, at a hardware module, indication of a load of a system; (ii) determining, by the hardware module, a voltage level and a clock signal frequency to be provided to the system; and (iii) configuring, by a software module, a voltage source and a clock signal source in response to the determination.

Abstract: An electronic device including a shielded electronic element, and a method for manufacturing a shielding structure. An oxide film is formed on the surface of a silicon substrate having a [100] face. Part of the oxide film is removed to form a first window region. Silicon substrates are joined together to form an SOI substrate, which includes a buried mask having a second window region. Substrate thinning is then performed, and oxide films are formed on the two surfaces of the SOI substrate so that the first window region has a large area and includes the region above the buried second window region. Then, anisotropic etching is performed to form a cap that includes a step. Wire bonding for shielding is performed on the step.

Abstract: A power switch circuit includes a first switch transistor connected to a main power supply, which supplies a first voltage, a second switch transistor connected in series to the first switch transistor and to a backup power supply, which supplies a second voltage. A switch control unit controls activation and deactivation of the first and second switch transistors so that either one of a voltage corresponding to the first voltage and a voltage corresponding to the second voltage is selectively output to a connection node between the first and second transistors. The first switch transistor includes a first diode, which is formed so that a direction from the main power supply toward the connection node defines a forward direction, and a second diode, which is formed so that a direction from the connection node toward the backup power supply defines a forward direction.

Abstract: A system and method is disclosed for providing single antenna interference cancellation processing with minimum latency. Incoming data frames are processed to generate a plurality of parallel data streams which are then further processed using a parallel single antenna interference cancellation algorithm to reject the signals and to generate a data stream containing only the desired symbols. In various embodiments of the invention, the parallel data streams are processed using a parallel arithmetic logic unit that is capable of operating in single-cycle mode in response to a first control stream and a multi-cycle mode in response to a second control stream. Embodiments of the invention comprise a three port memory interface operable to receive the parallel data streams and to generate a virtual three-dimensional data structure therefrom.

Abstract: A method for allocating memory that is associated with a CAN (controller area network) controller, comprises receiving a data frame comprising an identifier (ID) and data; dynamically allocating a message buffer (MB) within the memory for queuing the data frame; and generating a pointer that points to the MB, where the pointer is accessed via a static location in the memory. A corresponding host interface for the CAN controller can be implemented in IC circuitry, is configured to be coupled to a host CPU and a CAN bus interface, and includes a memory allocation unit for dynamic memory allocation and a memory access controller, coupled to the memory allocation unit and the memory, that is configured to control access to the memory to facilitate transmitting and receiving a multiplicity of data frames over a CAN bus.

Abstract: Improved Schottky diodes with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path of a first conductivity type serially located between a first terminal comprising a Schottky contact and a second terminal. The current path lies (i) between multiple substantially parallel finger regions of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact, and (ii) partly above a buried region of the second conductivity type that underlies a portion of the current path, which regions are electrically coupled to the first terminal and the Schottky contact and which portion is electrically coupled to the second terminal. When reverse bias is applied to the first terminal and Schottky contact the current path is substantially pinched off in vertical or horizontal directions or both, thereby reducing the leakage current and improving the breakdown voltage of the device.

Abstract: A method of forming a semiconductor layer, which in one embodiment is part of a photodetector, includes forming a silicon shape, applying ozonated water, removing the first oxide layer at a temperature below 600 degrees Celsius, and epitaxially growing germanium. The silicon shape has a top surface that is exposed. The ozonated water is applied to the top surface and causes formation of a first oxide layer on the top surface. The germanium is grown on the top surface.

Abstract: An electronic device as described herein implements a scheme to secure a data mapping function from scan access. The protection scheme can be used as a security measure for proprietary lookup tables, secret constants, digitally implemented algorithms, and the like. The electronic device employs a reconfigurable data mapping arrangement that can be reconfigured for a normal operating mode and a scan testing mode. While in the normal operating mode, a normal data mapping arrangement generates valid output data in accordance with the data mapping function. While in the scanning mode, however, a scanning data mapping arrangement generates invalid but testable output data in accordance with a data masking function that conceals, hides, masks, or obfuscates the data mapping function. Using the data masking function in this manner protects the data mapping function against reverse engineering attacks that attempt to derive the data mapping function from scan testing results.

Abstract: A wake-up control system comprises a plurality of different signal analyzer units. The plurality of different signal analyzer units may process a value of a different parameter of an incoming signal received at an input of a receiver and provide a false wake-up indication for the parameter when the value of the parameter is outside an acceptance range for the value. The system further comprises an evaluation unit connected to the plurality of different signal analyzer units for receiving the false wake-up indications. The evaluation unit may provide a false wake-up parameter information identifying an identified parameter of the different parameters when a sum of the false wake-up indications is outside an occurrence range for the false wake-up indications for the identified parameter.

Abstract: A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic.

Abstract: An integrated circuit comprises a delta-sigma modulator incorporating a delta-sigma modulation loop having an analog-to-digital converter in a forward path and a digital-to-analog converter in a feedback path such that the ADC is arranged to receive samples of an analog input signal. The ADC is operably coupled to auto-ranging logic arranged to shift a digital output signal from the ADC representative of the analog input signal to counteract an effect of an input variation of the analog input signal. In this manner, the application of auto-ranging logic with a self-recovery technique supports a reduction of the number of comparators required in a multi-bit delta-sigma ADC.

Abstract: A method includes forming a semiconductor structure, the semiconductor structure includes a first current electrode region, a second current electrode region, and a channel region, the channel region is located between the first current electrode region and the second current electrode region, wherein the channel region is located in a fin structure of the semiconductor structure, wherein a carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. The method further includes forming a first contact, wherein forming the first contact includes removing a first portion of the semiconductor structure to form an opening, wherein the opening is in the first current electrode region and forming contact material in the opening.

Abstract: An integrated circuit can be made more secure by programming a one time programmable circuit so that different signals are provided on terminals as compared to when the integrated circuit was not secure. Instead, or in addition, the integrated circuit can be made more secure by providing decode circuitry that can be used with the one time programmable circuit to select different internal address maps in response to an address value. The decode circuitry can use a first address map when the integrated circuit is secure, and a different address map when the integrated circuit is non-secure.

Abstract: Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, where the input is configured to receive the data signal. The output buffer is configured to produce an output signal based on the data signal, and the output signal has a maximum potential. The N-type transistor has a source coupled to the output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a bias potential, where the bias potential is greater than the maximum potential.

Abstract: A device and method for adjusting an impedance of an output driver of an integrated circuit; the method includes: (i) receiving, by the output driver, a first square wave signal that should be driven by the output driver to provide a second signal; (ii) monitoring, by a monitoring circuit included in the integrated circuit, the second signal during an output driver transient period resulting from a first square wave signal transient to provide a monitoring result; (iii) determining whether to adjust the impedance of the output driver in response to the monitoring result; and (iv) adjusting the impedance of the output driver in response to the determination.

Abstract: An assembly for producing partially packaged semiconductor devices is provided. In one embodiment, the assembly includes a magnetic plate; a flexible substrate disposed adjacent the magnetic plate and having two surfaces; a nonstick coating disposed on one surface of the flexible substrate thereby exposing a nonstick surface; and a tape layer having two surfaces. The tape layer is adhesively attached to the nonstick surface to expose a surface of the tape layer. A frame is disposed on the exposed surface of the tape layer, and a plurality of integrated circuit (IC) die is positioned within the frame and supported by the tape layer. A panel is formed within the frame that at least partially surrounds the plurality of IC die and that contacts the tape layer.