Abstract: A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel.

Abstract: A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.

Abstract: A method of de-interlacing input video information including averaging odd lines and averaging even lines of the input video information to determine first and second in-field information, determining differences between even and odd lines of the input video information to provide residue information, measuring a motion metric of the residue information, filtering the residue information based on the motion metric to provide filtered residue information, and combining the first and second in-field information with the filtered residue information to provide progressive information. The combining may be an average of the in-field information added to a weighted portion of the filtered residue information as determined by the motion metric. The motion metric may be determined by an infinite impulse response filter. Finite impulse response filters may be used to filter the residue information.

Abstract: A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.

Abstract: In a wireless 802.15.4 communication system (300), a high-speed data frame structure (340) is provided which uses the 802.15.4 SHR structure that is spread modulated to obtain the synchronization benefits of the 802.15.4 protocol, but which uses a modified data frame structure for the payload portion without using spreading to thereby improve its transmission efficiency. The transmission efficiency can be further increased by increasing the size of the data payload (and correspondingly, the frame length size).

Abstract: A method of storing data from a plurality of processors comprising the steps of (a) transferring data along a first bus (b) connectable between a first processor and a synchronizing means and operable with a first protocol; (c) synchronizing the synchronizing means with a second processor; and (d) transferring the data along a second bus to a memory of the second processor wherein the second bus is connectable between the synchronizing means and the memory of a second processor and operable with a second protocol.

Abstract: A data processing system and method generates debug messages by permitting an external debug tool to have real-time trace functionality. A data processor executes a plurality of data processing instructions and uses a memory for information storage. Debug circuitry generates debug messages including address translation trace messages. A memory management unit has address translation logic for implementing address translation to translate addresses between virtual and physical forms. The debug circuitry includes message generation circuitry that is coupled to the memory management unit for receiving notice when one or more address translation mappings are modified. The message generation circuitry generates an address translation trace message in response to a detection of a modification of an address translation mapping occurs and provides the address translation trace message external to the debug circuitry.

Abstract: A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.

Abstract: An amplifier circuit on a single die comprises a low voltage amplifier with a first common mode voltage and having an input and an output. A power amplifier has a second common mode voltage whose input is operably coupled to an output of the low voltage amplifier. The first common mode voltage and second common mode voltage are unequal. A compensation circuit is operably coupled to an input of the power amplifier and arranged to inject a DC-current or apply a common mode voltage into the power amplifier that is representative of a difference between the first common mode voltage and the second common mode voltage.

Abstract: A data processing apparatus is provided that includes a processing unit for processing data, including receiving data packets from a sender and sending acknowledgements to the sender, the processing unit having a first and second mode of operation for processing data, in which the second mode of operation requires more power than the first mode, and the processing unit switches between the first and second modes of operation based on a processing load; a metric module for determining a metric indicative of the processing load; an acknowledgement module for sending one acknowledgement in respect of n received data packets; and an acknowledgement configuration module for setting n to be a value m greater than a first predetermined value if the metric lies in a predetermined range that includes a value that the metric assumes when the processing unit switches between the first mode of operation and the second mode of operation, and to the first predetermined value otherwise.

Abstract: Methods of recovering symbols and corresponding communication receivers including dual receivers configured to perform the method, where the method comprises: sampling a received signal that includes interference to provide received samples; determining a plurality of high power symbols and determining alternate symbols for a portion of the plurality of high power symbols based on the received samples and based on known training symbols; and deriving a sequence of recovered symbols corresponding to the received samples based on the received samples and augmented training symbols, the augmented training symbols comprising the known training symbols augmented by the plurality of high power symbols with one or more alternate symbols replacing a corresponding one or more high power symbols.

Abstract: An electronic device and a method of packaging an electronic device are disclosed. In one embodiment, the electronic device can include a first die. The electronic device can also include a dielectric layer defining a first opening. The first die can be disposed within the first opening. Further, the electronic device can include an encapsulating material disposed adjacent to the first die. The encapsulating material can have a different composition as compared to the dielectric layer. In a particular embodiment, the electronic device can also include an electrically conductive carrier contacting the dielectric layer and the encapsulating material.

Abstract: A method of fabricating highly reliable tungsten interconnects takes into consideration the effects of charging that can occur within a CMP apparatus due to unrestricted DI water flow, limited only by house supply. Such effects are addressed with the use of a variable pressure input constant flow output in-line controller to the DI water line coupled to the head cleaning loading and unloading module of the CMP apparatus.

Abstract: A sensor device determines a value based on a sensed parameter by applying a voltage across two voltage terminals of a sensor. In response, the sensor provides an electrical signal representative of a sensed parameter to a controller via a pair of conductors. The controller samples the electrical signal to determine the value. In addition, the controller alternates the polarity of the voltage applied to the voltage terminals, thereby reducing the risk of damage to the conductors due to ion drift.

Abstract: Embodiments of the disclosure provide a system and method for providing channel feedback information (CFI) from a user equipment device to a base station. CFI is transmitted from the user equipment device on first and second communication channels. The user equipment device is operable to measure the channel rank of a downlink channel and to select a preferred channel rank that is used to configure the CFI that is transmitted to the base station. The base station is operable to use the preferred channel rank to interpret the CFI transmitted by the user end device.

Abstract: A configurable receiver and a method for configuring a receiver, the method includes: (i) evaluating multiple nonzero taps allocations, wherein each nonzero taps allocation evaluation includes: (i.a) allocating nonzero taps between multiple sparse equalizers, wherein different sparse equalizers are expected to equalize signals transmitted over different channels; wherein each channel is associated with an information source out of multiple information sources and with a receiving antenna out of multiple receiving antennas; wherein the number of nonzero taps is bounded by a upper limit; and (i.b) calculating multiple channel reception parameters of the multiple channels in response to the nonzero taps allocation; and (ii) configuring the receiver in response to a comparison between reception parameters obtained during different nonzero taps allocations.

Abstract: A receiver system, which generates a soft decision signal from a hard decision signal, includes a hard output receiver for determining a received bit to generate a hard decision signal. A hard input soft output receiver determines an estimated probability of symbol data corresponding to the received bit based on the hard decision signal and generates a soft decision signal represented by a log-likelihood ratio from the estimated probability.

Abstract: A method and a device having synchronizing capabilities, the device includes; (i) a first circuit that is adapted to receive a first clock signal; (ii) a second circuit that is adapted to receive a second clock signal; wherein the first and second clock signals and mutually asynchronous; and a (iii) synchronizer that is coupled between the first and second circuit and is adapted to receive the second clock signal, to receive an input signal from the first circuit and to output an output signal of definite values to the second circuit, wherein the input signal is synchronized with the first clock signal and the output signal is synchronized with the second clock signal.

Abstract: A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

Abstract: A bus driver has a ground terminal and a first and a second terminal. In a first operation mode the bus driver provides at the first terminal a first output voltage comprising a first data signal; and at the second terminal the bus driver provides a second output voltage comprising a second data signal. In a second operation mode the bus driver provides at the first terminal a first output voltage comprising a third data signal; and at the second terminal the bus driver provides a second output voltage, wherein a curve of the second output voltage is synchronous however inverted in relation to a curve of the first output voltage. An engine comprises a bus driver as set out above.