Abstract: Embodiments include shielded multi-layer packages for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.

Abstract: A PLL receives an indicator indicating that it is to operate at a different operating frequency than a current operating frequency. A control word is selected from a set of linear control words based upon the different operating frequency. A capacitance of a variable capacitor of a voltage-controlled oscillator is adjusted based upon the control word. The variable capacitor is monotonic and non-linear relative to the set of linear control words.

Abstract: A system that includes at least one component adapted to execute at least one application, characterized by including a controller adapted to receive at least one load indication of at least one component of the system and to selectively alter at least one control parameter of a voltage and clock frequency management scheme; whereas the system is adapted to apply the voltage and clock frequency management scheme. A method for controlling voltage level and clock frequency supplied to a system, the method includes receiving at least one load indication of at least one component of the system; characterized repeating the stages of: selectively altering at least one control parameter of a voltage and clock frequency management scheme; and applying the voltage and clock frequency management scheme.

Abstract: In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second numbers, respectively, with a count value from a counter to generate first and second signals, respectively. A multiplexer can receive the first and second signals at inputs and can receive the clock signal at a selection input. The multiplexer can output an output signal, as a divided clock signal, based on the clock signal, the first signal, and the second signal, where the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.

Abstract: A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, which corresponds to a baseline jitter amount. In turn, the receive test accelerator tests the device, at the adjusted test time, using a data stream that is modulated by the adjusted jitter amount.

Abstract: A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of the seed layer extends over a portion of the substrate; (c) removing the second portion of the seed layer; and (d) depositing a metal (215) over the first portion of the seed layer by an electroless process.

Abstract: A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal.

Abstract: A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.

Abstract: A device includes an array of cells, the source regions of the individual cells comprising a plurality of source region branches each extending towards a source region branch of an adjacent cell, the base regions of the individual cells comprising a corresponding plurality of base region branches merging together to form a single base region surrounding the source regions. The junctions between the merged base region and the drain region define rounded current conduction path areas for the on-state of the device between adjacent cells. Floating voltage regions of opposite conductivity type to the drain region are buried in the substrate beneath the merged base region. The features of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths of respective cells. The floating voltage regions include respective islands situated within the current conduction paths.

Abstract: A power source provides an output voltage to drive a plurality of light emitting diode (LED) strings. A feedback controller monitors the tail voltages of the LED strings to identify the minimum tail voltage and adjusts the output voltage based on a relationship between the minimum tail voltage and a reference voltage. The feedback controller implements precharging of the output voltage, including one or both of short-term precharging or long-term precharging. Further, the feedback controller incorporates a track/hold circuit that tracks the minimum tail voltage while the LED strings are active and holds the minimum tail voltage at the last tracked minimum tail voltage while the LED strings are inactive and uses the held minimum tail voltage for controlling the output voltage while the LED strings are inactive so as to permit the power source to supply an appropriate output voltage when the LED strings are subsequently activated again.

Abstract: An integrated circuit comprising oscillator circuitry is arranged to generate a clock signal for functional logic module of the integrated circuit. The oscillator circuitry comprises a plurality of propagation paths, and is arranged to apply a transition signal to inputs of the plurality of propagation paths, and to cause the output clock signal to transition based on a propagation of the transition signal through a determined set of the propagation paths.

Abstract: Methods and devices for scanning an incoming datastream for a plurality of target patterns. The scanning system receives an incoming data stream and stores the stream as sequential symbols in a register array. Previously received symbols are shifted in the array as incoming symbols are shifted in. A trigger stage computes a hash value based on the k most recently received symbols. The trigger stage then uses the hash value to determine whether a more detailed symbol by symbol comparison is required between a group of sequential symbols stored in the array and a target pattern stored in external storage. This is done by comparing the hash value with the indices of the target patterns in the external storage. If the more detailed comparison is indicated, a full comparison stage retrieves the relevant target pattern and compares the target pattern with the sequentially stored symbols in the array.

Abstract: A switch controller has a charge pump, a selector switch connected to the charge pump, and a pre-charge power supply input connectable to the input of the selector switch. For each of the output channels being controlled, a power control switch is connected to an output of the selector switch. In response to commands, output channels are enabled and disabled, causing corresponding actions in the power control switches. When an output channel is to be activated, the output channel is selected by the selector switch and the pre-charge power supply connected to the input of the selector switch. The charging is completed by the charge pump and the enabled status of the power control switch is maintained by the charge pump.

Abstract: Electronic elements (44, 44?, 44?) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44?, 44?) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36?) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62?, 62?) having electrically isolated inclusions (65, 65?, 65?) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78?, 78?) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65?, 65?) and silicon oxide for the dielectric material (78, 78?, 78?).

Abstract: Systems and methods are provided for controlling headroom of an amplifier (e.g., in a transmitter). A method comprises obtaining a target output power for a current interval and obtaining a target headroom for a subsequent interval. The method continues by adjusting, during the current interval, the power output capability of the amplifier based on the target headroom and adjusting the input power of an input signal based on the target output power, such that the output power of the amplifier is substantially constant during the current interval as the power output capability of the amplifier is adjusted.

Abstract: A method of grouping interrupts from a time-dependent data storage means in accordance with the types of the interrupts, the method comprising the steps of providing each part of the data storage means with an indicator of an event associated with the part, generating interrupts upon the occurrence of events in different parts of the data storage means, allocating interrupts associated with substantially the same part of the data storage means to a same processing means.

Abstract: Embodiments include transmitters, wireless devices, and methods for performing loop delay and gain control. In a transmitter, a gain application element receives and combines digital input samples and a digital gain signal to generate gain-compensated digital samples. A power amplifier receives and amplifies an analog version of the gain-compensated digital samples to generate an antenna output signal. A feedback path generates an analog feedback signal from the antenna output signal, to produce a sequence of digital feedback samples from the analog feedback signal, and generates the digital gain signal from the sequence of digital feedback samples and a loop gain estimate. A loop delay and gain calculator calculates a loop delay estimate from the gain-compensated digital samples and the sequence of digital feedback samples, and calculates the loop gain estimate using the loop delay estimate, the gain-compensated digital samples, and the sequence of digital feedback samples.

Abstract: An audio communication unit comprises a receiver for receiving an audio signal, a sigma-delta modulator operably coupled to the receiver and arranged to modulate the received audio signal, and a class-D amplifier stage operably coupled to the sigma-delta modulator and arranged to amplify the modulated received audio signal. One or more feedback path(s) is/are arranged from an output of the class-D amplifier stage to the sigma-delta modulator. The provision of one or more feedback path(s) from the output of the class-D audio amplifier to the sigma-delta modulator facilitates smaller die size; higher power efficiency and power supply rejection ratio/intermodulation cancellation performance.

Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134).

Abstract: A method includes determining, at a first requesting component of an integrated circuit device, a first key value based on a first set of one or more bits of a first address associated with a first access request of the first requesting component. The method further includes transmitting the first key value from the first requesting component to a resource component of the integrated circuit device. The method also includes determining, at the resource component, an authorization of the first access request based on the first key value and a second set of one or more bits of the first address.