Abstract: A multimode voltage regulator comprises an output for providing a regulator output voltage Vdd and an output current to a load and a low power reference voltage source having a reference voltage output providing the regulator output voltage Vdd, when in a first low power mode the output current is not greater than a threshold value. It may comprise a buffer amplifier having an output providing the regulator output voltage Vdd, when the output current is greater than the threshold value and a first bias voltage input being connected in a second low power mode to the reference voltage output when the output current is greater than the threshold value for less than a predefined time. And it may comprise a mode controller for automatically determining the output current and automatically switching from first low power mode to second low power mode.

Abstract: A device receives a request for an amount of a resource. It determines for each resource provider in a set of resource providers a current load, a requested load corresponding to the requested amount of the resource, and an additional load corresponding to an expected state of an application. It determines for each of the resource providers an expected total load on the basis of the current load, the requested load, and the additional load. It subsequently selects from the set of resource providers a preferred resource provider on the basis of the expected total loads. The resource may be one of the following: memory, processing time, data throughput, power, and usage of a device.

Abstract: A direct conversion receiver (200) includes a low noise amplifier (LNA) (213), at least one baseband amplifier (119, 123 and 127), register banks (250 and 251) for storing a plurality of offset data corresponding to at least two LNA gain settings and a plurality of baseband gain settings, a DC offset correction system (235) for providing a DC offset signal, a state machine (275) for sequencing through each of the plurality of baseband gain settings and through enable and disable states for the LNA, and a processor (290) programmed to activate the state machine and to run the DC offset correction system.

Abstract: A burn-in system (10) includes an enclosure (12) defining a burn-in chamber (14). The enclosure (12) is configured to be mounted on a burn-in board (34) over a burn-in socket (36). A heating element (16) is configured to generate heat within the burn-in chamber (14) and a temperature sensor (18) is configured to sense a temperature within the burn-in chamber (14). An opening (24) is formed in the enclosure (12) for receiving a fluid (26). A controller (20) is configured to control the heating element (16) and fluid flow into the enclosure (12) in response to the temperature sensed by the temperature sensor (18).

Abstract: A method is provided for transmitting data. A first device generates a first signal having a first duty cycle, comprising a first gated-on portion and a first gated-off portion in a time slot; and a second device generates a second signal having second duty cycle, comprising a second gated-on portion and a second gated-off portion in the same time slot. The first gated-on portion is generated during a first segment of the time slot and the first gated-off portion is generated during a second segment of the time slot, while the second gated-on portion is generated during the second segment and the second gated-off portion is generated during the first segment. Media access control (MAC) can be used to further define positions within time slots and provide error correction, power control, and the like. A preamble can be transmitted at an increased power level to facilitate acquisition.

Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.

Abstract: A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.

Abstract: An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.

Abstract: A method for testing an integrated circuit, that includes: (a) providing a first signal to a first path that starts within the integrated circuit and ends at a first memory element that is followed by a first IO pad, and providing a second signal to a second path that starts within the integrated circuit and ends at a second memory element that is followed by a second IO pad; (b) comparing between a first test result and a second test result, wherein the first test result represents a state of the first memory element sampled a predefined period after a provision of the first signal and the second test result represents a state of the second memory element sampled a predefined period after a provision of the second signal; (c) altering the predefined period; and (d) repeating the stages of providing, comparing and altering until detecting a time difference between a first path propagation period and a second path propagation period.

Abstract: A device and a method for processing a frame, the method includes: receiving a frame; retrieving a lookup key parse command that includes an instruction field and an bitmap representative of selected frame fields to be searched in the frame; generating a lookup key by extracting at least one frame field if the type of the received frame matches an expected frame type; and looking up, using the lookup key, for additional frame processing instructions.

Abstract: A communication system comprises a twisted pair communication link operably coupled to at least two driver stages for providing at least two independent input signals on the twisted pair communication link. The at least two independent input signals on the twisted pair communication link are summed and input to a comparator arranged to compare the summed signal to a reference value. The output of the comparator is input to the at least two driver stages. The outputs from the at least two driver stages are summed and fed back and summed with one or more of the independent input signals. In this manner, adverse effects due to non-ideal symmetry between components in a twisted pair communication link, such as a Controller Area Network system, are reduced.

Abstract: Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations include one with possible data and another that is empty. Determining which of the two, if at all, have experienced brownout includes using two different sense references. One has a higher standard for detecting a logic high and the other higher standard for detecting a logic low. Results from using the two different references are compared. If the results are the same for both references, then there is no brownout. If the results are different for either there has been a brownout. The location with the different results is set to an invalid state as the location that has experienced the brownout.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: A device for providing a constant output voltage based on a variable input voltage is provided. The device may include: (1) a charge-pump comprising a plurality of cells, wherein each of the plurality of cells can be configured as an input cell, a stepping cell, or a load cell; (2) a comparator; and (3) a differentiator coupled to the comparator output, wherein the differentiator is configured to monitor the comparator output and produce a reset pulse each time the comparator output changes its state. The device may further include: (1) a decimator; (2) an up/down counter; and (3) a controller for detecting whether the device is operating in a first predetermined mode or a second predetermined mode, wherein the two modes relate to the configuration of the plurality of cells into the input cell, the stepping cell, and/or the load cell.

Abstract: A communication unit comprises a controller and a radio frequency signal path having a plurality of delay elements operably coupled to a series of respective amplifier stages, wherein the controller is arranged to individually enable the respective amplifier stages. In response thereto a number of the plurality of delay elements are selectively inserted into or by-passed from the radio frequency signal path thereby adjusting a phase shift applied to signals provided through the radio frequency signal path.

Abstract: An embodiment of a calibration standard includes a substrate, a set of conductive structures fabricated on the substrate, and a conductive end structure fabricated on the substrate. The set of conductive structures include an inner conductive structure, a first outer conductive structure positioned to one side of the inner conductive structure, and a second outer conductive structure positioned to an opposite side of the inner conductive structure. The inner and outer conductive structures are aligned in parallel with each other along offset principal axes of the inner and outer conductive structures. The conductive end structure is electrically connected between an end of the first outer conductive structure and an end of the second outer conductive structure, and the conductive end structure is spatially separated from an end of the inner conductive structure at the surface of the substrate.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

Abstract: A module has a substrate, first and second integrated circuits, and a heat sink. The integrated circuits each have a first major surface, a second major surface, a first edge, a second edge, and a third edge and have optical circuits having ports on the first edge and electronic circuits having ports on the second edge. The second edges are connected to the substrate. The first major surface of the second integrated circuit is parallel with the second major surface of the first integrated circuit. The heat sink has a backplane adjacent to the third edge, a first portion along the first major surface of the first integrated circuit, a second portion along the second major surface of the second integrated circuit extending from the backplane, and an insert between the first major surface of the second integrated circuit and the second major surface of the first integrated circuit.

Abstract: A method of manufacturing a semiconductor package, where the package includes a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface. The method is characterised in that it comprises the step of patterning one or more channels on the surface which channels extend away from the joint area towards an edge of the surface. Also the method has the step of applying a compound to one or more channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the interaction defines one or more paths in the connective material. These correspond to the one or more channels on the surface and allow the passage of waste material away from the joint area to the outer edge of the surface.

Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.